Chapter 5: Detailed Description of EISA Bus

Chapter 5

The Previous Chapter

The previous chapter provided a detailed description of interrupt handling in the EISA environment.

This Chapter

This chapter provides a description of all the signals on the EISA bus.

The Next Chapter

In the next chapter, the types of bus cycles performed by the main CPU and EISA bus masters are described.

Introduction

The EISA bus consists of two sets of signal lines:

•the ISA Bus

•the extension to the ISA Bus (the EISA bus extension)

Figure 5-1 illustrates the construction of the EISA connector. When installed, ISA boards are physically stopped by the EISA access key and make contact only with the ISA contacts. When an EISA board is installed, however, an alignment notch in the board allows it to bottom out, making contact with both the ISA and the EISA contacts.

41

EISA System Architecture

ISA contacts

EISA contacts

EISA access key

Figure 5-1. The EISA Connector

Many of the ISA signals have already been defined in preceding sections of this book and all of them are fully defined in the MindShare book entitled ISA System Architecture. This section is confined to a description of the EISA signals. The following are the signal groups that comprise the EISA Bus.

•Address bus extension

•Data bus extension

•Bus Arbitration signal group

•Burst handshake signal group

•Bus cycle definition signal group

42

Chapter 5: Detailed Description of EISA Bus

•Bus cycle timing signal group

•Lock signal

•Slave size signal group

•AEN signal

The following paragraphs provide a description of each of these signal groups.

Address Bus Extension

One of the restrictions imposed by the ISA bus structure is a function of the width of the address bus. It consists of 24 address lines, A[23:0]. This permits the microprocessor to address any memory location between address 000000h and FFFFFFh, a range of 16MB.

With the advent of multi-tasking, multi-user operating systems, access to a greater amount of memory became an imperative. The EISA specification expands the address bus to 32 bits (A31:0]), and also adds the byte enable lines, BE#[3:0], to provide 32-bit bus master address support. The ISA bus includes the following address lines:

•SA[19:0]

•LA[23:17]

•SBHE#

The EISA address bus consists of the following signals:

•SA[1:0] (ISA bus)

•SBHE# (ISA bus)

•LA[23:17] (ISA bus)

•LA#[31:24] (EISA extension)

•BE#[3:0] (EISA extension)

•LA[16:2] (EISA extension)

The EISA specification extends the size of the LA Bus to include LA[16:2] and LA#[31:24]. Refer to figure 5-2. Combined with the previously-defined SA bus and LA signal groups on the ISA portion of the bus, this extends the address bus to a full 32-bits, allowing the current bus master to generate any memory address in the range 00000000h – FFFFFFFFh. This is a range of 4GB (giga = billion).

43

EISA System Architecture

Figure 5-2. The EISA Connector Address Lines

LA#[31:24] are asserted low to prevent 16-bit bus masters from inadvertently selecting 32-bit memory cards residing above 16 MB. When a 16-bit bus master places an address on the address bus, it is only using lines A[23:0]. If address lines LA#[31:24] were allowed to float, a 32-bit memory card that resides above the 16MB boundary might be inadvertently selected. Rather, LA#[31:24] are pulled high with pull-up resistors on the system board, ensuring that they are deasserted unless asserted by a 32-bit bus master. 32-bit EISA memory cards

44