Chapter 11: Bridge, Translator, Pathfinder, Toolbox

two slave types. This enables any bus master type to communicate with devices of any other type. Table 11-4 indicates the signal lines used by each of the three bus master and slave types to indicate address phase, data phase and the bus cycle type.

Table 11-4. Command Lines

				Address
	Device			Phase
	Type			Signal			Data Phase Signal			Bus Cycle Type Indicators
	EISA			START#			CMD#			M/IO# and W/R#
	ISA			BALE			SMRDC#, SMWTC#,			SMRDC#, SMWTC#, MRDC#,
							MRDC#, MWTC#, IORC#,			MWTC#, IORC#, IOWC#
							IOWC#
	Host			ADS#			End of ADS# until			W/R#, M/IO# and D/C#
							READY# sampled active

Pathfinder

Under some circumstances, data path steering is necessary. When a bus master is communicating with a slave using a data path or paths that the slave is incapable of using, the data bus steering logic must be activated. During a read bus cycle, the data bus steering logic ensures that the returning data arrives at the bus master on the expected data path(s). During a write bus cycle, the data bus steering logic ensures that the data being written by the bus master is routed to the data path(s) that the slave expects to receive the data on. In an EISA machine, the data bus steering function is provided by the EISA chipset. Table 11- 5 defines the situations when data bus steering is necessary. A more detailed description of data bus steering may be found in the MindShare book entitled ISA System Architecture. The 32-bit bus master or a 16-bit EISA bus master indicates the data path(s) to be used during a bus cycle using its byte enable outputs, BE#[3:0]. A 16-bit ISA bus master uses A0 and BHE# to indicate the data path(s) that will be used during a bus cycle. The addressed slave indicates the data path(s) that it is connected to by asserting IO16#, M16#, EX16# or EX32#. If IO16#, M16# or EX16# is asserted by the currently-addressed slave, it is a 16-bit device and is connected to data paths 0 and 1. If the currently-addressed slave asserts EX32#, it is a 32-bit device and is connected to all four data paths. If none of these lines are asserted, the addressed slave is an 8-bit device and is connected only to path 0.

129

EISA System Architecture

Table 11-5. Situations Requiring Data Bus Steering

	Bus						Bus
	Master			Slave			Cycle
	Type			Type			Type			Steering Action Required
	32-bit			8-bit			write			When a 32-bit bus master is writing a single byte to an 8-
										bit device over paths 1, 2, or 3, the data bus steering
										logic must copy the byte down to path 0 so it can get to
										the 8-bit device. When a 32-bit bus master is writing
										multiple bytes to an 8-bit device in a single bus cycle,
										the data bus steering logic must route the data to path 0
										one byte at a time. As each byte is routed to the lower
										data path, the address seen by the 8-bit device must be
										incremented by the steering logic and the MWTC# or
										IOWC# line must be turned off and then on again to
										trick the 8-bit device into thinking another bus cycle has
										been initiated.
	32-bit			8-bit			read			When a 32-bit bus master is reading a single byte from
										an 8-bit device over path 1, 2, or 3, the data bus steering
										logic must copy the byte from path 0 to the path the bus
										master expects to receive the byte on. When a 32-bit bus
										master is attempting to read multiple bytes from an 8-bit
										device in a single bus cycle, the 8-bit device can only
										return one byte at a time. The steering logic must ad-
										dress each byte individually, copy it to the proper data
										path and latch it in a latching data bus transceivers until
										all of the requested bytes have been retrieved. As each
										byte is routed to and latched by the proper data bus
										transceiver, the address seen by the 8-bit device must be
										incremented by the steering logic and the MRDC# or
										IORC# line must be turned off and then on again to trick
										the 8-bit device into thinking another bus cycle has been
										initiated.
	32-bit			16-bit			write			When a 32-bit bus master is writing one or two bytes to
										a 16-bit device over paths 2 or 3, the data bus steering
										logic must copy the byte or bytes to path 0 and/or path
										1 so that they can get to the 16-bit device.

130

Chapter 11: Bridge, Translator, Pathfinder, Toolbox

										Table 11 - 5 cont.
	Bus						Bus
	Master			Slave			Cycle
	Type			Type			Type			Steering Action Required
	32-bit			16-bit			read			When a 32-bit bus master is reading one or two bytes
										from a 16-bit device over paths 2 or 3, the data bus steer-
										ing logic must copy the byte or bytes from path 0
										and/or path 1 to path 2 and/or path 3 so that they are
										received by the bus master over the expected data
										path(s).
	32-bit			32-bit			read			none
							or
							write
	16-bit			8-bit			write			When a 16-bit bus master is writing a single byte to an 8-
										bit device over path 1, the data bus steering logic must
										copy the byte down to path 0 so that it can get to the 8-
										bit device. When a 16-bit bus master is writing two bytes
										to an 8-bit device in a single bus cycle, the data bus
										steering logic must route the data to path 0 one byte at a
										time. As each byte is routed to the lower data path, the
										address seen by the 8-bit device must be incremented by
										the steering logic and the MWTC# or IOWC# line must
										be turned off and then on again to trick the 8-bit device
										into thinking another bus cycle has been initiated.
	16-bit			16-bit			read			none
							or
							write
	16-bit			32-bit			write			When a 16-bit bus master is writing one or two bytes to
										either of the last two locations in a doubleword in a sin-
										gle bus cycle, the steering logic must copy the byte or
										bytes to path 2 and/or path 3 so that the data will be
										routed to the proper location(s) within the addressed
										doubleword.
	16-bit			32-bit			read			When a 16-bit bus master is reading one or two bytes
										from either of the last two locations in a doubleword in
										a single bus cycle, the steering logic must route the byte
										or bytes from path 2 and/or path 3 to path 0 and/or
										path 1 so that the data will be received over the proper
										path(s).

131

EISA System Architecture

Toolbox

In addition to providing the bridge, translation and data bus steering functions, the EISA chipset includes a toolbox with all of the basic support elements necessary for the proper function of any EISA system. These include:

•Two modified Intel 8259A programmable interrupt controllers in a master/slave configuration

•Two modified Intel 8237 DMA controllers in a master/slave configuration

•The refresh logic

•The central arbitration control

•Five programmable timers

•The NMI logic

Detailed descriptions of interrupts, DMA, refresh, the timers and the NMI logic can be found in the MindShare book entitled ISA System Architecture. Information regarding the EISA-specific enhancements to the interrupt, DMA, refresh and the NMI control logic can be found earlier in this book. Information regarding the Central Arbitration Control (CAC) can be found earlier in this publication. A description of the Intel 82357 Integrated Systems Peripheral (ISP) can be found in the next chapter. The ISP, part of the Intel EISA chipset, contains all of the above-mentioned logic elements.

132