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Shanley T.EISA system architecture.1995.pdf
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EISA System Architecture

Figure 12-1 illustrates the relationship of the Intel EBC, ISP, Data Buffer and Address Buffer to the host, EISA/ISA and X-buses in the 82350 environment.

 

 

Host Bus

 

 

 

 

 

 

 

 

 

 

Data

 

82358

 

Address

 

82357

Buffer

 

 

 

 

EBC

 

Buffer

 

(Data Bus

 

 

 

ISP

Steering)

 

 

 

 

 

 

 

 

 

 

 

 

 

EISA/ISA Bus

X-Bus

Buffer

X Bus

Figure 12-1. The Intel EISA Chipset

EISA Bus Controller (EBC) and EISA Bus Buffers (EBBs)

General

The EBC is pictured in figure 12-2. Together with the Data and Address EBBs, the EBC provides the bridging, translation and data bus steering functions described in the previous chapter. The following sections describe each of the functional areas that comprise the EBC.

134

Chapter 12: Intel 82350DT EISA Chipset

CPU Selection

These four inputs to the EBC indicate the host CPU type and its bus frequency. Table 12-1 defines the valid settings for these inputs. If the host CPU is integrated onto the system board, these pins should be permanently strapped to the appropriate state. When the host CPU resides on a plug-in card, however, the four CPU signals should be set to the appropriate state when the CPU card is inserted. This allows automatic configuration of the EBC to match the CPU card installed in the machine. CPU input patterns not specified in table 12-1 are reserved for future use.

Table 12-1. CPU Type/Frequency

 

CPU3

 

 

CPU2

 

 

CPU1

 

 

CPU0

 

 

CPU Type/Frequency

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

1

 

0

 

 

32-bits, 2x clock, 25MHz 80386

 

 

1

 

0

 

1

 

1

 

 

32-bits, 2x clock, 33MHz 80386

 

 

1

 

1

 

0

 

0

 

 

32-bits, 1x clock, 25MHz 80486

 

 

1

 

1

 

0

 

1

 

 

32-bits, 1x clock, 33MHz 80486

 

135

EISA System Architecture

To Data Buffer

Data

Buffer

 

Control

 

 

 

 

 

Address

To Address Buffer

Buffer

 

Control

 

 

 

 

 

Host Bus

Host Bus

Interface

Unit

 

 

 

 

 

Host Cache

Cache

Support

 

 

 

 

Reset Logic

Reset

Control

 

 

 

 

 

CPU

CPU Select Lines

Select

 

 

AENLE#

Slot-Specific

I/O Support

 

Clock

Generator

Unit

ISA Bus

Interface

Unit

EISA Bus

Interface

Unit

ISP

Interface

Unit

I/O

Recovery

Logic

Test

Support

Clock Logic

ISA Bus

EISA Bus

ISP

LIOWAIT#

TEST1#

Figure 12-2. The Intel 82358DT EBC

136

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