- •About This Book
- •Chapter 1: EISA Overview
- •Introduction
- •Compatibility With ISA
- •Memory Capacity
- •Synchronous Data Transfer Protocol
- •Enhanced DMA Functions
- •Bus Master Capabilities
- •Data Bus Steering
- •Bus Arbitration
- •Edge and Level-Sensitive Interrupt Requests
- •Automatic System Configuration
- •EISA Feature/Benefit Summary
- •Chapter 2: EISA Bus Structure Overview
- •Chapter 3: EISA Bus Arbitration
- •EISA Bus Arbitration Scheme
- •Preemption
- •Example Arbitration Between Two Bus Masters
- •Memory Refresh
- •Chapter 4: Interrupt Handling
- •ISA Interrupt Handling Review
- •ISA Interrupt Handling Shortcomings
- •Phantom Interrupts
- •Limited Number of IRQ Lines
- •EISA Interrupt Handling
- •Shareable IRQ Lines
- •Phantom Interrupt Elimination
- •Chapter 5: Detailed Description of EISA Bus
- •Introduction
- •Address Bus Extension
- •Data Bus Extension
- •Bus Arbitration Signal Group
- •Burst Handshake Signal Group
- •Bus Cycle Definition Signal Group
- •Bus Cycle Timing Signal Group
- •Lock Signal
- •Slave Size Signal Group
- •AEN Signal
- •EISA Connector Pinouts
- •Chapter 6: ISA Bus Cycles
- •Introduction
- •8-bit ISA Slave Device
- •16-bit ISA Slave Device
- •Transfers With 8-bit Devices
- •Transfers With 16-bit Devices
- •Standard 16-bit Memory ISA bus Cycle
- •Standard 16-bit I/O ISA bus Cycle
- •ISA DMA Bus Cycles
- •ISA DMA Introduction
- •8237 DMAC Bus Cycle
- •Chapter 7: EISA CPU and Bus Master Bus Cycles
- •Intro to EISA CPU and Bus Master Bus Cycles
- •Standard EISA Bus Cycle
- •General
- •Analysis of EISA Standard Bus Cycle
- •Performance Using EISA Standard Bus Cycle
- •Compressed Bus Cycle
- •General
- •Performance Using Compressed Bus Cycle
- •General
- •Analysis of EISA Burst Transfer
- •Performance Using Burst Transfers
- •DRAM Memory Burst Transfers
- •Downshift Burst Bus Master
- •Chapter 8: EISA DMA
- •DMA Bus Cycle Types
- •Introduction
- •Compatible DMA Bus Cycle
- •Description
- •Performance and Compatibility
- •Type A DMA Bus Cycle
- •Description
- •Performance and Compatibility
- •Type B DMA Bus Cycle
- •Description
- •Performance and Compatibility
- •Type C DMA Bus Cycle
- •Description
- •Performance and Compatibility
- •EISA DMA Transfer Rate Summary
- •Other DMA Enhancements
- •Addressing Capability
- •Preemption
- •Buffer Chaining
- •Ring Buffers
- •Transfer Size
- •Chapter 9: EISA System Configuration
- •ISA I/O Address Space Problem
- •EISA Slot-Specific I/O Address Space
- •EISA Product Identifier
- •EISA Configuration Registers
- •EISA Configuration Process
- •General
- •Configuration File Naming
- •Configuration Procedure
- •Configuration File Macro Language
- •Example Configuration File
- •Example File Explanation
- •Chapter 10: EISA System Buses
- •Introduction
- •Host Bus
- •EISA/ISA Bus
- •Chapter 11: Bridge, Translator, Pathfinder, Toolbox
- •Bus Cycle Initiation
- •Bridge
- •Translator
- •Address Translation
- •Command Line Translation
- •Pathfinder
- •Toolbox
- •Chapter 12: Intel 82350DT EISA Chipset
- •Introduction
- •EISA Bus Controller (EBC) and EISA Bus Buffers (EBBs)
- •General
- •CPU Selection
- •Data Buffer Control and EISA Bus Buffer (EBB)
- •General
- •Transfer Between 32-bit EISA Bus Master and 8-bit ISA Slave
- •Transfer Between 16-bit EISA Bus Master and 8-bit ISA Slave
- •Transfer Between 16-bit ISA Bus Master and 8-bit ISA Slave
- •Transfer Between 16-bit ISA Bus Master and 16-bit ISA Slave
- •Transfer Between 32-bit Host CPU and 32-bit Host Slave
- •Transfer Between 32-bit Host CPU and 8-bit ISA Slave
- •Transfer Between 32-bit Host CPU and 16-bit ISA Slave
- •Transfer Between 32-bit Host CPU and 16-bit EISA Slave
- •Transfer Between 32-bit Host CPU and 32-bit EISA Slave
- •Address Buffer Control and EBB
- •Host CPU Bus Master
- •EISA Bus Master
- •ISA Bus Master
- •Refresh Bus Master
- •DMA Bus Master
- •Host Bus Interface Unit
- •ISA Bus Interface Unit
- •EISA Bus Interface Unit
- •Cache Support
- •Slot-Specific I/O Support
- •Clock Generator Unit
- •I/O Recovery
- •Testing
- •ISP interface unit
- •82357 Integrated System Peripheral (ISP)
- •Introduction
- •NMI Logic
- •Interrupt Controllers
- •DMA Controllers
- •System Timers
- •Central Arbitration Control
- •Refresh Logic
- •Miscellaneous Interface Signals
- •Glossary
- •Index
EISA System Architecture
Figure 12-1 illustrates the relationship of the Intel EBC, ISP, Data Buffer and Address Buffer to the host, EISA/ISA and X-buses in the 82350 environment.
|
|
Host Bus |
|
|
|
|
|
|
|
|
|
|
|
Data |
|
82358 |
|
Address |
|
82357 |
Buffer |
|
|
|
|||
|
EBC |
|
Buffer |
|
||
(Data Bus |
|
|
|
ISP |
||
Steering) |
|
|
|
|
|
|
|
|
|
|
|
|
|
EISA/ISA Bus
X-Bus
Buffer
X Bus
Figure 12-1. The Intel EISA Chipset
EISA Bus Controller (EBC) and EISA Bus Buffers (EBBs)
General
The EBC is pictured in figure 12-2. Together with the Data and Address EBBs, the EBC provides the bridging, translation and data bus steering functions described in the previous chapter. The following sections describe each of the functional areas that comprise the EBC.
134
Chapter 12: Intel 82350DT EISA Chipset
CPU Selection
These four inputs to the EBC indicate the host CPU type and its bus frequency. Table 12-1 defines the valid settings for these inputs. If the host CPU is integrated onto the system board, these pins should be permanently strapped to the appropriate state. When the host CPU resides on a plug-in card, however, the four CPU signals should be set to the appropriate state when the CPU card is inserted. This allows automatic configuration of the EBC to match the CPU card installed in the machine. CPU input patterns not specified in table 12-1 are reserved for future use.
Table 12-1. CPU Type/Frequency
|
CPU3 |
|
|
CPU2 |
|
|
CPU1 |
|
|
CPU0 |
|
|
CPU Type/Frequency |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1 |
|
0 |
|
1 |
|
0 |
|
|
32-bits, 2x clock, 25MHz 80386 |
|
|||
|
1 |
|
0 |
|
1 |
|
1 |
|
|
32-bits, 2x clock, 33MHz 80386 |
|
|||
|
1 |
|
1 |
|
0 |
|
0 |
|
|
32-bits, 1x clock, 25MHz 80486 |
|
|||
|
1 |
|
1 |
|
0 |
|
1 |
|
|
32-bits, 1x clock, 33MHz 80486 |
|
135
EISA System Architecture
To Data Buffer |
Data |
|
Buffer |
||
|
Control |
|
|
|
|
|
|
|
|
Address |
|
To Address Buffer |
Buffer |
|
|
Control |
|
|
|
|
|
|
|
|
Host Bus |
|
Host Bus |
Interface |
|
Unit |
||
|
||
|
|
|
|
|
|
Host Cache |
Cache |
|
Support |
||
|
|
|
|
|
|
Reset Logic |
Reset |
|
Control |
||
|
|
|
|
|
|
|
CPU |
|
CPU Select Lines |
Select |
|
|
|
|
AENLE# |
Slot-Specific |
|
I/O Support |
||
|
Clock
Generator
Unit
ISA Bus
Interface
Unit
EISA Bus
Interface
Unit
ISP
Interface
Unit
I/O
Recovery
Logic
Test
Support
Clock Logic
ISA Bus
EISA Bus
ISP
LIOWAIT#
TEST1#
Figure 12-2. The Intel 82358DT EBC
136