Table 12 - 6, cont.
	EISA System Architecture
	HSTRETCH#	input		Host Bus Stretch. This input can be used by host
				bus slaves during EISA/ISA or DMA bus master
				cycles to stretch the low part of BCLK during
				CMD# (data time). This has the effect of stalling the
				EISA/ISA master without adding BCLK wait
				states.
	HKEN#	input		Host Cache Enable. When sampled active, indi-
				cates that the host CPU is requesting a cache line
				fill operation.

ISA Bus Interface Unit

The ISA interface unit pictured in figure 12-2 observes bus cycles initiated by ISA bus masters. The ISA bus interface unit awaits completion of the bus cycle. If either the host CPU or an EISA bus master is addressing an ISA slave, the ISA interface unit runs a bus cycle. When the bus cycle on the ISA bus is completed, EXRDY or HRDYO# is sent to the EISA or host bus master to terminate the bus cycle. Table 12-7 provides a description of the ISA interface signals. For a complete description of the ISA bus, refer to the MindShare book entitled ISA System Architecture.

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Table 12-7. ISA Interface Unit Signal Descriptions

	Signal			Direction			Description
	BALE			output			Bus Address Latch Enable. During an ISA bus cy-
							cle, BALE is set high at the midpoint of address time
							and dropped low at the end of address time. The
							address is gated from the LA bus to the SA bus
							when BALE goes high and is latch when BALE goes
							low at the end of address time.
	SA0, SA1,			input/output			Least-significant part of the ISA address bus. These
	BHE#						are inputs when the bus cycle is being run by an ISA
							bus master and outputs when the bus cycle is being
							run by an EISA or host master.
	IORC#			input/output			The I/O Read Command line. Generated by an ISA
							bus master when it is performing an I/O read bus
							cycle. When an EISA or host bus master is perform-
							ing an I/O read bus cycle, the EBC's ISA interface
							unit generates this signal.
	IOWC#			input/output			The I/O Write Command line. Generated by an ISA
							bus master when it is performing an I/O write bus
							cycle. When an EISA or host bus master is perform-
							ing an I/O write bus cycle, the EBC's ISA interface
							unit generates this signal.
	MRDC#			input/output			The Memory Read Command line. Generated by
							an ISA bus master when it is performing a memory
							read bus cycle. When an EISA or host bus master is
							performing a memory read bus cycle, the EBC's ISA
							interface unit generates this signal.
	MWTC#			input/output			The Memory Write Command line. Generated by
							an ISA bus master when it is performing a memory
							write bus cycle. When an EISA or host bus master is
							performing a memory write bus cycle, the EBC's ISA
							interface unit generates this signal.
	SMRDC#			output			Standard Memory Read Command line. The EBC's
							ISA interface unit generates this signal when any
							bus master is reading from memory space in the
							00000000h – 000FFFFFh range. A memory address
							decoder located in the ISP chip generates GT1M#
							whenever it detects a memory address in this range,
							causing the ISP interface unit to generate either
							SMRDC# or SMWTC#.
						Table 12 - 7, cont.

177

EISA System Architecture

SMWTC#	output	Standard Memory Write Command line. The EBC's
		ISA interface unit generates this signal when any
		bus master is writing to memory space in the
		00000000h – 000FFFFFh range. A memory address
		decoder located in the ISP chip generates GT1M#
		whenever it detects a memory address in this range,
		causing the ISP interface unit to generate either
		SMRDC# or SMWTC#.
IO16#	input/output	IO Size 16. Generated by a 16-bit ISA I/O slave
		when addressed by a bus master. Set active by the
		EBC's ISA interface unit when an ISA bus master is
		addressing a host I/O slave (HLOCIO# sampled
		active). EISA slaves that support ISA bus masters
		must assert IO16# as well as EX16# or EX32# when
		addressed.
M16#	input	Memory Size 16. Generated by a 16-bit ISA memory
		slave when addressed by a bus master.
NOWS#	input	No Wait States. An ISA slave may generate NOWS#
		when it has decoded its address and a read or write
		command line has been activated. When set active
		by the slave, it conditions the default ready timer (in
		the ISA interface unit) to set ready active at the end
		of the current BCLK. It is used to shorten the num-
		ber of wait states appended to a bus cycle by the
		default ready timer.
CHRDY	input/output	Channel Ready. If an ISA slave requires more time
		to complete a bus cycle than allowed by the default
		ready timer, it may set the CHRDY line low. This
		prevents the default ready timer from timing out
		until the slave is ready to end the bus cycle. When
		the slave is ready to end the bus cycle, it sets
		CHRDY active again, permitting the default ready
		timer to time out.
REFRESH#	input	Generated by the Refresh logic in the ISP chip when
		the Refresh logic is bus master and is performing a
		refresh bus cycle.
MASTER16#	input	16-bit Bus Master. Generated by either ISA or 16-bit
		EISA bus master when it initiates a bus cycle.

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EISA Bus Interface Unit

The EISA interface unit pictured in figure 12-2 observes bus cycles initiated by EISA bus masters. The EISA bus interface unit awaits completion of the bus cycle. If either the host CPU or an ISA bus master is addressing an EISA slave, the EISA interface unit runs a bus cycle. Table 12-8 provides a description of the EISA interface signals. For a complete description of the EISA bus, refer to earlier sections of this publication.

Table 12-8. EISA Interface Unit Signal Descriptions

	Signal			Direction			Description
	BE#[3:0]			input/output			Byte Enable lines. Set to the appropriate states during
							a bus cycle initiated by an EISA bus master. When an
							ISA master initiates a bus cycle, the EBC's EISA inter-
							face unit converts SA0, SA1 and SBHE# to the corre-
							sponding setting on the BE lines. When the host CPU
							initiates a bus cycle, the state of the host byte enables
							lines, HBE#[3:0], are passed onto the EISA byte enable
							lines by the EBC.
	M/IO#			input/output			Memory or I/O bus cycle definition line. Generated by
							an EISA master or by the EBC when the host CPU or
							an ISA master is performing a bus cycle.
	W/R#			input/output			Write or Read bus cycle definition line. Generated by
							an EISA master or by the EBC when the host CPU or
							an ISA master is performing a bus cycle.
	LOCK#			output			Generated by the EBC when the host CPU is bus mas-
							ter and has asserted HLOCK# to the EBC. An active
							level on the EISA LOCK# line prevents other bus mas-
							ters from requesting the buses until LOCK# goes
							away.
	START#			input/output			Set active by an EISA bus master when it initiates a
							bus cycle and deactivated at the end of address time.
							Controlled by the EBC when an ISA master or the host
							CPU is performing a bus cycle to signal the start of the
							bus cycle on the EISA bus. Also controlled by the EBC
							during DMA transfers and under some conditions
							requiring data bus steering.
	CMD#			output			Command. Set active by the EBC at the start of data
							time and kept active until the end of the bus cycle.
					Table 12 - 8, cont.

179