Chapter 6: ISA Bus Cycles

Chapter 6

The Previous Chapter

The previous chapter provided a functional description of the EISA bus signals.

This Chapter

This chapter provides a brief review of the ISA bus master and DMA bus cycles. For a detailed description of this subject matter, refer to the MindShare book entitled ISA System Architecture.

The Next Chapter

The next chapter provides a detailed description of the EISA CPU and bus master bus cycle types.

Introduction

In order to define extensions to ISA, the writers of the EISA specification had to first document ISA. The following descriptions of ISA bus cycles are based on the descriptions found in the EISA specification.

The Bus Clock (BCLK) is supplied to the ISA bus by the system board and defines the time slots (Tstates) that comprise a bus cycle. In order to maintain ISA compatibility, the maximum clock rate used for bus cycles on the EISA bus is 8.33MHz.

8-bit ISA Slave Device

An 8-Bit ISA slave device interfaces only to the least-significant eight data bus bits and uses only ISA address bus bits SA[19:0]. This is the simplest and slowest of the slave devices and was first developed for use with the IBM PC. These devices didn't have to be very fast because the PC was based on an Intel 8088 microprocessor running at 4.77MHz.

53

EISA System Architecture

At 4.77MHz, the clock period is 209.64ns and a 0-wait state bus cycle consists of four clock cycles (838.6ns). In other words, devices with an access time of up to 836ns could be interfaced to the microprocessor without incurring any wait states. Since the designer must account for the cycle time of DRAMs (typically double the access time), not the stated access time, this means that DRAMs with an access time of up to 400ns could be interfaced to the microprocessor without incurring wait states.

16-bit ISA Slave Device

A 16-bit ISA slave device interfaces to sixteen ISA data bus bits and uses ISA address bus lines SA[19:0], LA[23:17] and SBHE#. 16-bit devices were developed for use with the IBM PC-AT. Some of these devices were designed to operate in the original 6MHz version of the IBM PC-AT, while most were designed to work with the 8MHz version.

The 6MHz PC-AT could interface with a slave device having an access time of up to approximately 332ns and incur no wait states. This being the case, DRAMs with an access time of up to approximately 165ns could be accessed with 0-wait states.

The 8MHz PC-AT could interface with a slave device having an access time of up to approximately 250ns and incur no wait states. DRAMs with an access time of up to approximately 125ns could therefore be accessed with 0-wait states.

Transfers With 8-bit Devices

The ISA bus cycle types utilized to communicate with 8-bit devices include:

•Standard 8-bit device ISA bus cycle – four wait states

•Shortened 8-bit device bus cycle – one, two, or three wait states

•Stretched 8-bit device bus cycle – more than four wait states

The steps that follow describe the sequence of events that take place during an 8-bit bus cycle using the default READY# timing and explains how the default timing can be either shortened or stretched. Figure 6-1 illustrates an example bus cycle. The step numbers in the text that follows corresponds to the numbered reference points in figure 6-1.

54

Chapter 6: ISA Bus Cycles

1.The address being presented by the current bus master begins to appear on the LA bus at the start of the address phase. This corresponds to the leading edge of Ts. If the system board is based on an 80286 or 80386 microprocessor and address pipelining is asserted, the address may actually be present on the LA bus prior to the beginning of the bus cycle (as is the case in this example). 16-bit ISA memory expansion cards can use the portion of the address on the LA bus to perform an early address decode. 8-bit ISA expansion cards do not have access to the LA bus and therefore cannot perform an early address decode. I/O cards only use the lower 16 address bits and therefore cannot take advantage of address pipelining.

2.BALE is asserted half-way through the address phase, gating the address through the system board address latch onto the SA bus.

3.If this is a write bus cycle, the microprocessor's write data is gated onto the SD bus half-way through the address phase. It remains on the SD bus until half a BCLK cycle into the next bus cycle (half-way through the address phase of the next transfer).

4.The trailing-edge of BALE (at the beginning of the first data clock period) causes the system board address latch to latch the address being output by the CPU so that it remains static on the SA bus for the remainder of the bus cycle. The addressed slave device can safely complete the decoding process during this period.

5.If this is a memory transaction and the M16# signal is sampled deasserted by the system board bus control logic at the end of the address phase, the command line (SMRDC# or SMWTC#) is not activated until half-way through the first data clock period. If this is an I/O transaction, I/O16# will not be sampled until reference point seven to determine if the currentlyaddressed device is an 8 or a 16-bit device.

6.If this is a memory transaction and M16# was sampled deasserted at the end of the address phase, M16# is again sampled half-way through the first data clock period. The continued deasserted state of M16# indicates that the addressed expansion board is an 8-bit device.

7.The appropriate command line (SMRDC#, SMWTC#, IORC# or IOWC#) is asserted half-way through the first data clock period. During a transfer with an 8-bit device, the activation of the command line is delayed until the midpoint of the first data clock period to allow more time for address decode before command line activation. The command line then remains asserted until the end of the bus cycle (end of last Tc).

8.If this is an I/O transaction, the IO16# signal is sampled deasserted by the system board bus control logic, indicating that the addressed expansion board is an 8-bit device.

9.Half-way through the second data clock period and half-way through each subsequent data clock period, the default ready timer on the system board

55

EISA System Architecture

samples the NOWS# line. If sampled asserted, the CPU READY# line is activated and the bus cycle ends on the next rising-edge of BCLK (the end of the current data clock period). In this way, an ISA board can terminate a bus cycle earlier than the default number of BCLK cycles (wait states) by activating NOWS#.

10.This item does not have a corresponding numbered reference point on the timing diagram. A bus cycle addressing an 8-bit ISA device defaults to six BCLK cycles (four wait states) if the following two conditions are met:

a)the bus cycle isn't terminated earlier by the assertion of NOWS#.

b)CHRDY is asserted when sampled during the first half of the last data clock period of the default cycle (first half of the 5th data clock period).

This causes the duration of an ISA bus cycle when accessing an 8-bit device to default to four wait states (unless shortened by NOWS# to three, four, or five BCLK cycles, or lengthened by the deassertion of CHRDY. The bus cycle ends at the trailing-edge of the fifth data clock period.

11.During a read bus cycle, the microprocessor reads the data on the data bus at the trailing-edge of the last data clock period (Tc) of the bus cycle and the bus cycle is then terminated. The command line (SMRDC#, IORC#, etc.) is de-activated at that time. When a write bus cycle terminates, the MWTC#, SMWTC# or IOWC# command line is de-activated. Write data remains on the SD bus until half-way through the address phase of the next bus cycle. This accommodates the hold time of the device being written to and doesn't disturb the device being addressed in the next bus cycle because the command line for that bus cycle hasn't been activated yet.

56