EISA System Architecture

ISA Interrupt Handling Shortcomings

Phantom Interrupts

Internally, the 8259 has a pull-up resistor on each of its IRQ inputs. When an ISA expansion card must generate an interrupt request, the line is driven low by the card and is then allowed to go high again. The low-to-high transition is registered as an interrupt request by the 8259 interrupt controller on the system board. The 8259 specification also demands that the IRQ line must remain high until after the leading-edge of the first interrupt acknowledge bus cycle generated by the host processor. The pull-up resistor ensures that this will be the case.

Consider the case where an ISA card is designed to keep its IRQ line low until a request must be generated. At that time, the card would allow the IRQ line to go high and would maintain the high until the request has been serviced. The transition from low-to-high would be registered as a request by the 8259. When the request has been serviced, the card would drive the line low again and keep it low until the next request is to be generated. Although this design would work, a problem may arise.

A transitory noise spike on this interrupt request line could register as a valid interrupt request. When the microprocessor issues the first of the two interrupt acknowledge bus cycles, however, the IRQ line will already be low again. This means that the IRQ line's respective IRR (Interrupt Request Register) bit will not be active. The first interrupt acknowledge resets the highest-priority IRR bit and sets its associated bit in the ISR (In-Service Register). In this case, since the IRR bit is no longer set because the request was of too short a duration (a ghost, or phantom, interrupt), the 8259 must take special action. The 8259 is designed to automatically return the interrupt vector for its number seven input in this case. When the microprocessor then generates the second interrupt acknowledge, the 8259 sends back the vector associated with its number seven input. On the system’s master 8259, this is 0Fh, the vector of IRQ7. On the slave, it is 77h, the IRQ15 interrupt vector. The microprocessor therefore jumps to either the IRQ7 or the IRQ15 interrupt service routine.

In these two routines, therefore, the programmer must perform a check to see if the IRQ7 or the IRQ15 was real. This is accomplished by reading the contents of the respective 8259's ISR register and checking to see if bit seven is really set. If it is, then the request is real and the programmer should execute the remainder of the interrupt service routine to service the request. If, on the other hand, the

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