EISA System Architecture

and CHRDY to determine when the ISA slave is ready to end the byte transfer. The EBC turns off SDCPYEN02# and SDOE2# to turn off the copy transceiver and the cause the path two latch in the data EBB to stop outputting the second data byte.

Both bytes have now been transferred to the 8-bit ISA slave. The EBC now activates HRDYO#, host ready output, to tell the host CPU that it's ok to end the bus cycle.

Transfer Between 32-bit Host CPU and 16-bit ISA Slave

The EBC recognizes that the host CPU is performing a bus cycle when HHLDA, Host Hold Acknowledge, is inactive and HADS0# and HADS1# are set active. The HADSx# lines are connected to the CPU's Host Address Status output. The host CPU places the address on HA[31:2] and sets the host byte enable lines, HBE#[3:0], to the appropriate state. The EBC causes the address EBB to broadcast the address onto the ISA and EISA address buses as well. In this example, assume that the host CPU is writing two bytes to a 16-bit ISA slave over host data paths two and three. This means that the host CPU is setting BE2# and BE3# active. SA1 is set high, while SA0 and SBHE# are set low. The host CPU indicates the type of bus cycle on HM/IO#, HW/R# and HD/C#.

Since a 16-bit ISA slave is being addressed, the EBC samples an active level on M16# or IO16#. The EBC latches the two bytes into the path two and three latches in the data EBB using its HDSDLE1# output. It then outputs the two bytes onto the EISA data bus by activating its SDOE2# output. The data bytes on EISA data paths two and three are copied down to paths zero and one when the EBC activates its SDCPYEN02# and SDCPYEN13# outputs and sets SDCPYUP low. The EBC monitors NOWS# and CHRDY to determine when the ISA slave is ready to end the transfer. The EBC turns off SDCPYEN02#, SDCPYEN13# and SDOE2# to turn off the copy transceiver and the cause the path two and three latches in the data EBB to stop outputting the two data bytes.

Both bytes have now been transferred to the 16-bit ISA slave. The EBC now activates HRDYO#, host ready output, to tell the host CPU that it's ok to end the bus cycle.

Transfer Between 32-bit Host CPU and 16-bit EISA Slave

The EBC recognizes that the host CPU is performing a bus cycle when HHLDA, Host Hold Acknowledge, is inactive and HADS0# and HADS1# are

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Chapter 12: Intel 82350DT EISA Chipset

set active. The HADSx# lines are connected to the CPU's Host Address Status output. The host CPU places the address on HA[31:2] and sets the host byte enable lines, HBE#[3:0], to the appropriate state. The EBC causes the address EBB to broadcast the address onto the ISA and EISA address buses as well. In this example, assume that the host CPU is writing two bytes to a 16-bit EISA slave over host data paths two and three. This means that the host CPU is setting BE2# and BE3# active. The EBC activates BE2# and BE3# on the EISA address bus. The host CPU indicates the type of bus cycle on HM/IO#, HW/R# and HD/C#.

Since a 16-bit EISA slave is being addressed, the EBC samples an active level on EX16#. The EBC latches the two bytes into the path two and three latches in the data EBB using its HDSDLE1# output. It then outputs the two bytes onto the EISA data bus by activating its SDOE2# output. The data bytes on EISA data paths two and three are copied down to paths zero and one when the EBC activates its SDCPYEN02# and SDCPYEN13# outputs and sets SDCPYUP low. The EBC monitors EXRDY to determine when the EISA slave is ready to end the transfer. The EBC turns off SDCPYEN02#, SDCPYEN13# and SDOE2# to turn off the copy transceiver and the cause the path two and three latches in the data EBB to stop outputting the two data bytes.

Both bytes have now been transferred to the 16-bit EISA slave. The EBC now activates HRDYO#, host ready output, to tell the host CPU that it's ok to end the bus cycle.

Transfer Between 32-bit Host CPU and 32-bit EISA Slave

The EBC recognizes that the host CPU is performing a bus cycle when HHLDA, Host Hold Acknowledge, is inactive and HADS0# and HADS1# are set active. The HADSx# lines are connected to the CPU's Host Address Status output. The host CPU places the address on HA[31:2] and sets the host byte enable lines, HBE#[3:0], to the appropriate state. The EBC causes the address EBB to broadcast the address onto the ISA and EISA address buses as well. In this example, assume that the host CPU is writing four bytes to a 32-bit EISA slave using all four host data paths. This means that the host CPU is setting all four host byte enable lines, HBE#[3:0], active. The EBC activates BE#[3:0] on the EISA address bus. The host CPU indicates the type of bus cycle on HM/IO#, HW/R# and HD/C#.

Since a 32-bit EISA slave is being addressed, the EBC samples an active level on EX32#. The EBC latches the four bytes into the data EBB's data latches using its HDSDLE1# output. It then outputs the four bytes onto the EISA data bus by activating its SDOE0#, SDOE1# and SDOE2# outputs. The EBC monitors EXRDY

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