Chapter 7: EISA CPU and Bus Master Bus Cycles

Chapter 7

The Previous Chapter

The previous chapter provided a review of bus master and DMA bus cycles in the ISA environment.

This Chapter

This chapter provides a detailed description of the EISA CPU and bus master bus cycle types.

The Next Chapter

The next chapter provides a detailed description of the EISA DMA bus cycle types.

Intro to EISA CPU and Bus Master Bus Cycles

In order to maintain complete ISA compatibility, ISA bus cycles are executed precisely as they are in an ISA machine. These bus cycle types have been described in the preceding chapter.

As stated earlier, an Intel x86-compatible processor is capable of executing seven types of bus cycles:

•Memory data read and memory instruction read. These two types are actually identical, reducing the total to six bus cycle types.

•Memory data write

•I/O data read

•I/O data write

•Interrupt acknowledge

•Halt or Shutdown (also referred to as the special cycle)

Of these six, only four are ever seen by the expansion boards on the ISA bus:

•Memory Read

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