Chapter 12: Intel 82350DT EISA Chipset

Chapter 12

The Previous Chapter

The previous chapter described the major functions performed by an EISA chipset.

This Chapter

This chapter provides an introduction to the Intel 82350DT EISA chipset. The focus is on the 82358DT EISA Bus Controller (EBC), the 82357 Integrated Systems Peripheral (ISP), and the 82352 EISA Bus Buffers (EBBs).

Introduction

This chapter is not intended as a substitute for the Intel publication that describes the 82350DT EISA chipset. It is intended as a companion to the Intel document, providing an introduction to the roles each component plays in a typical EISA system. Only the crucial chipset components are represented here: the EBC, the address EBB, the data EBB and the ISP. For detailed information, refer to the Intel document entitled “82350DT EISA Chipset,” order number 290377-002. The EBC can be configured to operate in three different types of environments:

•With the host interface unit interfaced directly to the host CPU subsystem. This is referred to as the 82350 environment.

•With the host interface unit interfaced to the host bus through the Intel 82359 DRAM controller. This is referred to as the 82350DT/enhanced environment.

•With the host interface unit interfaced to a buffered bus. The buffered bus, in turn, is connected to the Intel 82359 DRAM controller, which is connected to the host bus. This is referred to as the 82350DT/buffered environment.

This chapter describes operation of the EISA chipset configured for the 82350 environment.

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