Chapter 5: Detailed Description of EISA Bus

are designed to recognize that these upper address lines carry inverted address information (0 on a line is a logical 1 and a 1 is a logical 0).

Since the address information on the LA bus shows up sooner than the address on the SA bus (due to address pipelining and the fact that the LA bus bypasses the address latch on the system board), memory cards that use the LA lines can perform an early address decode. This allows the memory card designer to use slightly slow (inexpensive) memory chips and yet achieve higher throughput. In addition, the fact that the LA bus now includes the lower part of the address bus allows memory cards that use SCRAM or Page Mode RAM to determine if the next access will be in the same row of memory (because the row portion of the DRAM address is carried over the lower portion of the address bus).

The EISA specification also adds the four byte enable signal lines, BE#[3:0], allowing 32-bit bus masters to generate addresses in doubleword address format (A[31:2] plus the BE lines) and 32-bit slaves to see the address in 32-bit doubleword format.

Data Bus Extension

The EISA specification extends the width of the data bus by adding two additional data paths consisting of SD[23:16] and D[31:24]. Using these data paths plus the two ISA data paths allows 32-bit bus masters to transfer four bytes (a doubleword) during a single transfer when communicating with 32-bit slaves.

Bus Arbitration Signal Group

Under EISA, two signals have been added to allow implementation of bus master cards. They are described in table 5-1.

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EISA System Architecture

Table 5-1. EISA Bus Master Handshake Lines

	Signal Name			Full Name			Description
	MREQx#			Master Request for slot x			When a bus master in a slot requires
							the use of the bus to perform a trans-
							fer, it asserts its slot-specific MREQx#
							signal line. This signal is applied to the
							CAC on the system board, which then
							arbitrates its priority against other
							pending bus requests.
	MAKx#			Master Acknowledge for			When the CAC is ready to grant the
				slot x			bus to a requesting bus master
							(MREQx# is asserted), the CAC asserts
							the bus master's MAKx# slot-specific
							signal line to inform the bus master
							that it has been granted the bus.

Figure 5-3 illustrates the relationship of the master request and acknowledge lines to the CAC. The subject of bus arbitration is covered in detailed the chapter entitled “EISA Bus Arbitration.”

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Chapter 5: Detailed Description of EISA Bus

Figure 5-3. The Bus Master Handshake Lines

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EISA System Architecture

Burst Handshake Signal Group

The EISA specification adds two signal lines to support initiation of burst mode (Type C) bus cycles. They are described in table 5-2.

					Table 5-2. The Burst Handshake Lines
	Signal
	Name			Full Name			Description
	SLBURST#			Slave Burst			When addressed, a slave asserts SLBURST# to indi-
							cate that it supports burst cycles. If the slave supports
							burst cycles, it asserts this signal regardless of the
							state of the MSBURST# signal line.
	MSBURST#			Master Burst			During a bus cycle, the current bus master asserts
							this line as a response to the assertion of SLBURST#.
							This informs the addressed slave that the bus master
							supports burst cycles.

The subject of burst mode (Type C”) bus cycles is covered in detail in the chapter entitled “EISA CPU and Bus Master Bus Cycles.”

Bus Cycle Definition Signal Group

The EISA specification defines a new set of bus cycle definition signal lines. The current EISA bus master uses them to inform the currently addressed slave of the type of bus cycle in progress. Table 5-3 defines the new signals.

Table 5-3. EISA Bus Cycle Definition Lines

	Signal Name			Full Name			Description
	M/IO#			Memory or I/O			During a bus cycle, M/IO# is set high if a memory
							address is on the address bus. It is set low if it's an
							I/O address.
	W/R#			Write or Read			During a bus cycle, W/R# is set high if a write bus
							cycle is in progress and low if a read bus cycle is
							in progress.

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