Chapter 4: Interrupt Handling

Chapter 4

The Previous Chapter

The previous chapter described the bus arbitration scheme utilized in EISA machines.

This Chapter

An in-depth discussion of interrupt request handling in the ISA environment can be found in the chapter entitled “Interrupt Handling” in the MindShare book entitled ISA System Architecture. This chapter provides a brief review of the ISA interrupt request handling method and a detailed description of the EISA method.

The Next Chapter

The signals and support logic that comprise the ISA bus impose certain limitations on performance and capabilities. The EISA specification builds upon the ISA bus, adding new bus signals and system board support logic. The end result is backward-compatibility with all ISA cards and improved performance and capabilities for EISA cards. The next chapter provides a detailed description of the extensions to the ISA bus and support logic.

ISA Interrupt Handling Review

The Intel 8259 interrupt controller's interrupt request inputs can be programmed to recognize either a rising-edge or a static high level as a valid interrupt request. The programmer may select either of these recognition modes for all eight inputs at once. There is no provision for the selection of either type on an input-by-input basis. On an ISA machine, the 8259 interrupt controllers are programmed to recognize a rising-edge as a valid interrupt request on its eight inputs. The following section describes the two shortcomings inherent in ISA interrupt handling.

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