Chapter 3: EISA Bus Arbitration

Chapter 3

The Previous Chapter

The previous chapter provided background on ISA’s inability to support multiple processors in a fair fashion and introduced the EISA bus and the role of the Central Arbitration Control logic on the EISA system board. The types of bus masters and slaves were identified.

This Chapter

The bus arbitration scheme used by the EISA Central Arbitration Control is described in detail.

The Next Chapter

The next chapter, “Interrupt Handling,” describes the methods used to detect and service interrupt requests in both the ISA and EISA environments.

EISA Bus Arbitration Scheme

All EISA systems incorporate a device known as the Central Arbitration Control (CAC) on the system board. The CAC's task is to arbitrate among the outstanding requests for bus ownership and to then grant the bus to the winner.

There are four classifications of devices that can issue requests to the CAC:

•Main CPU

•Expansion bus masters

•Refresh controller on the system board

•DMA Controller (DMAC) on the system board

Figure 3-1 illustrates the CAC's relationship to potential bus masters.

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EISA System Architecture

Figure 3-1. Block Diagram of the Central Arbitration Control (CAC)

The CAC uses a multi-level, rotating priority arbitration scheme. Figure 3-2 depicts this rotational priority scheme. On a fully loaded bus, the order in which devices are granted bus access is independent of the order in which they generate bus requests, since devices are serviced based on their position in the ro-

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Chapter 3: EISA Bus Arbitration

tational order. The DMAC is given a high order of priority to assure compatibility with ISA expansion boards that require short bus latency (because they don’t have any buffering). The EISA bus masters are assigned a lower priority and designers of EISA bus master cards must therefore provide for longer bus latency by incorporating buffers.

The top priority level uses a 3-way rotation to grant bus access sequentially to a DMA channel, the refresh controller, and a device from the 2-way rotation (either the main CPU or a bus master card). A DMA channel, the refresh controller and a device from the 2-way rotation each gain access to the bus at least one of every three arbitration cycles (depending on what devices are requesting service). A device that does not request the bus is skipped in the rotation. The main CPU is allowed to retain control of the bus when no other devices are requesting bus mastership. In systems that provide the main CPU with a lookthrough cache controller, the host processor only requires the use of the bus under the following conditions:

•a cache read miss

•an I/O read or write

In a system wherein the main CPU doesn't have a cache (or uses a look-aside cache), the main CPU frequently requests the use of the bus.

The DMA controller is programmed during the POST to use a fixed priority scheme in evaluating which DMA channel to service next. As pictured in figure 3-2, this means that DMA channel zero has the highest priority, followed by channels two – seven. It should be noted that DMA channel four is unavailable because it is used to cascade the slave DMA controller through the master (see the chapter entitled “DMA and Bus Mastering” in the MindShare book entitled

ISA System Architecture).

NMI interrupts are given special priority (because NMI is used to report critical errors). When an NMI interrupt occurs, the arbitration mechanism is modified so that the bus master cards and the DMACs are bypassed each time they come up for rotation. This gives the CPU complete control of the bus for NMI servicing.

DMA priorities can be modified by programming the DMAC control register to use rotating priority. This scenario is pictured in figure 3-3. Each DMA channel then has essentially the same priority as all of the others.

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EISA System Architecture

Refresh

Highest		CPU
		or
Priority
DMA		Bus
Channel		Master

	Bus			CPU
Channel 0
	Masters
Channel 1
Channel 2
Channel 3
Channel 5
Channel 6		Bus
Channel 7	Master
		1
	Bus			Bus
	Master			Master
	n	2
	Bus			Bus
	Master			Master
	4	3

Figure 3-2. CAC with DMACs Programmed for Fixed Priority

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Chapter 3: EISA Bus Arbitration

Refresh

Next		CPU
		or
DMA
		Bus
Channel
		Master

		Channel		Channel		Bus				CPU
5				6
						Masters
		Master
		DMAC
		Channel		Channel
4
				7
		(cascade)
								Bus
							Master
								1
		Channel			Channel		Bus				Bus
						Master					Master
				1
0							n	2
				Slave
			DMAC
		Channel			Channel		Bus				Bus
							Master				Master
3				2
						4		3

Figure 3-3. CAC with DMACs Programmed for Rotational Priority

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