EISA System Architecture

Compatible DMA Bus Cycle

Description

Each of the seven DMA channels is default-programmed to use ISA-compatible DMA bus cycles to transfer data between an I/O device and memory. As in an ISA machine, channels zero – three are default-programmed for 8-bit transfers, while channels five – seven are default programmed for 16-bit transfers. Any DMA channel may be re-programmed to perform 8, 16, or 32-bit transfers using the ISA-compatible bus cycle.

When programmed to use ISA-compatible DMA bus cycles, a transfer is performed every eight BCLK periods. Table 8-1 defines the duration of key signals during an ISA-compatible DMA bus cycle.

Table 8-1. The DMA ISA-Compatible Bus Cycle

	Event			Duration
	Memory address present			8.0 BCLKs
	Duration of data transfer period during a memory to			4.5 BCLKs
	IO transfer (CMD# active)
	Duration of MRDC# during memory to IO transfer			4.5 BCLKs
	Duration of IORC# during I/O to memory transfer			6.5 BCLKs
	Duration of IOWC# during a memory to IO transfer			4.0 BCLKs
	Duration of MWTC# during I/O to memory transfer			4.0 BCLKs

The duration of the key signals illustrated in table 8-1 defines the amount of time the memory and I/O device have to recognize that they are being addressed and to either accept or output data. Comparing this table to the tables found in the sections on the other three DMA bus cycle types, it is clear that the amount of time allotted for address decode and data movement becomes increasingly shorter for the faster bus cycle types.

Performance and Compatibility

Table 8-2 defines the data transfer rates when a DMA channel is programmed to use the ISA-compatible DMA bus cycle to transfer data.

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