Chapter 5: Detailed Description of EISA Bus

Bus Cycle Timing Signal Group

Under the EISA specification, the signals described in table 5-4 were added to define the address and data portions of the bus cycle, as well as the end of the bus cycle.

					Table 5-4. EISA Bus Cycle Timing Signals
	Signal
	Name			Full Name				Description
	START#			Start phase				Every EISA bus cycle consists of two phases: the start
								and command phases. The address and the M/IO#
								control line are output by the current bus master and
								decoded by the target slave during the start phase.
								The start phase corresponds to address time and is
								therefore one BCLK is duration.
	CMD#			Command				Every EISA bus cycle consists of two phases: the start
				phase				and command phases. The data is transferred during
								the command phase. CMD# is asserted at the trailing
								edge of the START# signal (trailing edge of Ts) and
								stays asserted until the end of the bus cycle. When a
								bus cycle has wait states inserted, the CMD# signal
								remains asserted for multiple cycles of BCLK.
	EXRDY			EISA Ready				Deasserted by an EISA slave to request the insertion of
								wait states in the current bus cycle. It is sampled on
								each falling edge of BCLK after the CMD# line is as-
								serted. When sampled asserted, the bus cycle will be
								terminated at the next rising edge of BCLK.

Lock Signal

The LOCK# signal is asserted by the current bus master to prevent other bus masters from arbitrating for the use of the bus. This allows the current bus master to complete one or more memory accesses prior to surrendering control to another bus master. The purpose of the bus lock capability is to prevent two bus masters that share a memory location as a software semaphore from becoming de-synchronized with each other.

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EISA System Architecture

Slave Size Signal Group

When the current bus master addresses an EISA-style slave, the slave asserts one of these two signals to indicate the data paths it can use and to signal that it is an EISA-style slave. Table 5-5 describes these two signals.

Table 5-5. The EISA Type/Size Lines

	Signal
	Name			Full Name			Description
	EX32#			EISA Slave Size 32			When a 32-bit EISA slave decodes its address, it
							asserts EX32# to inform the current bus master
							that it can handle 32-bit transfers.
	EX16#			EISA Slave Size 16			When a 16-bit EISA slave decodes its address, it
							asserts EX16# to inform the current bus master
							that it can handle 16-bit transfers.

AEN Signal

The following paragraph describes the manner in which the AEN signal is used under the ISA specification.

When either the master or slave DMA Controller (DMAC) on the system board becomes bus master, it asserts AEN as a substitute for BALE, indicating that a valid memory address is present on the address bus. Memory cards then decode the address on the address bus. I/O cards also monitor the AEN signal line and ignore the address on the bus when AEN is asserted. This is necessary because the DMAC asserts either the IORC# or IOWC# line and I/O devices think that there is an I/O address on the bus when there really isn’t.

It should be noted that AEN has another, special, usage in the EISA environment. This additional function is discussed in the chapter entitled “EISA System Configuration.”

EISA Connector Pinouts

The EISA connector is an extended version of the ISA connector. The ISA connector is divided into an 8-bit connector and a 16-bit extension. In figure 5-4, the upper half of the EISA connector, rows A and B, comprise the 8-bit portion that is compatible with the IBM PC and XT expansion connector and the 8-bit

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Chapter 5: Detailed Description of EISA Bus

portion of the connector found in the IBM PC/AT. On the lower half of the EISA connector in the figure, rows C and D comprise the 16-bit portion that is compatible with the 16-bit extension to the 8-bit connector found in the IBM PC/AT. The pins on the EISA connector are arranged in eight rows. Rows A, B, C, and D comprise the ISA group, while rows E, F, G and H comprise the EISA group.

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EISA System Architecture

F1	GND
F2	+5
F3	+5
F4	xxxxxx
F5	xxxxxx
F6	key
F7	xxxxxx
F8	xxxxxx
F9	+12
F10	M/IO#
F11	LOCK#
F12	Reserved
F13	GND
F14	Reserved
F15	BE3#
F16	key
F17	BE2#
F18	BE0#
F19	GND
F20	+5
F21	LA29#
F22	GND
F23	LA26#
F24	LA24#
F25	key
F26	LA16
F27	LA14
F28	+5
F29	+5
F30	GND
F31	LA10

H1 LA8

H2 LA6

H3 LA5

H4 +5

H5 LA2

H6 key

H7 SD16

H8 SD18

H9 GND

H10 SD21

H11 SD23

H12 SD24

H13 GND

H14 SD27

H15 key

H16 SD29

H17 +5

H18 +5

H19 MAKx#

F B E A

B1 GND

B2	RESDRV
B3	+5
B4	IRQ9
B5	-5
B6	DRQ2
B7	-12
B8	NOWS#
B9	+12
B10	GND
B11	SMWTC#
B12	SMRDC#
B13	IOWC#
B14	IORC#
B15	DAK3#
B16	DRQ3
B17	DAK1#
B18	DRQ1
B19	REFRESH#
B20	BCLK
B21	IRQ7
B22	IRQ6
B23	IRQ5
B24	IRQ4
B25	IRQ3
B26	DAK2#
B27	TC
B28	BALE
B29	+5
B30	OSC
B31	GND
D1	M16#
D2	IO16#
D3	IRQ10
D4	IRQ11
D5	IRQ12
D6	IRQ15
D7	IRQ14
D8	DAK0#
D9	DRQ0
D10	DAK5#
D11	DRQ5
D12	DAK6#
D13	DRQ6
D14	DAK7#
D15	DRQ7
D16	+5
D17	MASTER16#

D18 GND

H D G C

E1	CMD#
E2	START#
E3	EXRDY
E4	EX32#
E5 GND
E6	key
E7	EX16#
E8	SLBURST#
E9	MSBURST#
E10	W/R#
E11	GND
E12	Reserved
E13	Reserved
E14	Reserved
E15	GND
E16	key
E17	BE1#
E18	LA31#
E19	GND
E20	LA30#
E21	LA28#
E22	LA27#
E23	LA25#
E24	GND
E25	key
E26	LA15
E27	LA13
E28	LA12
E29	LA11
E30	GND
E31	LA9

G1 LA7

G2 GND

G3 LA4

G4 LA3

G5 GND

G6 key

G7 SD17

G8 SD19

G9 SD20

G10 SD22

G11 GND

G12 SD25

G13 SD26

G14 SD28

G15 key

G16 GND

G17 SD30

G18 SD31

G19 MREQx#

A1 CHCHK#

A2 SD7

A3 SD6

A4 SD5

A5 SD4

A6 SD3

A7 SD2

A8 SD1

A9 SD0

A10 CHRDY

A11 AENx

A12 SA19

A13 SA18

A14 SA17

A15 SA16

A16 SA15

A17 SA14

A18 SA13

A19 SA12

A20 SA11

A21 SA10

A22 SA9

A23 SA8

A24 SA7

A25 SA6

A26 SA5

A27 SA4

A28 SA3

A29 SA2

A30 SA1

A31 SA0

C1 SBHE#

C2 LA23

C3 LA22

C4 LA21

C5 LA20

C6 LA19

C7 LA18

C8 LA17

C9 MRDC#

C10 MWTC#

C11 SD8

C12 SD9

C13 SD10

C14 SD11

C15 SD12

C16 SD13

C17 SD14

C18 SD15

Figure 5-4. The EISA Connector Pin Assignments

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