EISA System Architecture
			Bus Master Direction
			Host
			ISA
			EISA
	HALAOE#	B3_OE#
	LALE#	B23_LE#
	LAHAOE#	A_OE#	Upper
	HALE#	A_LE#
			Host/EISA
	HA2:HA31		Latching	LA24#:LA31#
			Transceiver
			Lower	LA2:LA23
			Host/EISA
			Latching
			Transceiver
		B012_OE#
		B01_LE#
	HM/IO#			M/IO#

Bus Master Direction

Host

ISA

EISA

EISA/ISA	SA2:SA19
Latching
Transceiver

LASAOE#	S_OE#
SALAOE#	SB_OE#
SALE#	S_LE#

Bus Master Direction

Host

ISA

EISA

Figure 12-5. Block Diagram of Address EBB

Host Bus Interface Unit

The host bus interface unit pictured in figure 12-2 observes bus cycles initiated by the host CPU. If neither HLOCMEM# nor HLOCIO# are sensed active, the host bus master is addressing a slave on the EISA or ISA bus. In this case, the host bus interface unit commands either the EISA or ISA interface unit in the EBC to run a bus cycle. The host bus interface unit awaits completion of the bus

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Chapter 12: Intel 82350DT EISA Chipset

cycle and sends ready to the host CPU. Table 12-6 provides a description of the host bus interface signals. The description of these signals assumes that the EBC is configured for the 82350 environment. To configure the EBC for the 82350 environment, two conditions must be met:

•The AMODE input must be strapped low.

•The HNA#/SBMODE# input is sampled on the leading-edge of the SPWROK input. To select the 82350 configuration, it must be sampled high.

Table 12-6. Host Interface Unit Signal Descriptions

	Signal			Direction			Description
	AMODE			input			Address Mode. Configures the EBC for 82350
							mode when strapped low; for 82350DT mode when
							strapped high.
	HBE#[3:0]			input/output			Host Byte Enables. When the host CPU is bus mas-
							ter, these inputs define the target location(s) within
							the addressed doubleword. The EBC's ISA inter-
							face unit converts them to SA0, SA1 and SBHE# on
							the ISA address bus, while the EBC's EISA inter-
							face unit converts them to BE#[3:0] on the EISA
							address bus.
							When an EISA bus master has initiated a bus cycle,
							the state of the BE#[3:0] lines on the EISA address
							bus are output onto the HBE#[3:0] lines on the host
							address bus.
							When an ISA bus master has initiated a bus cycle,
							the state of the SA0, SA1 and SBHE# lines on the
							ISA address bus are converted and output onto the
							HBE#[3:0] lines on the host address bus.
	HADS0# and			input			Host Address Status 0 and 1. The host CPU or the
	HADS1#						host cache controller's ADS# output is connected to
							the HADS0# input. ADS# indicates that it is ad-
							dress time and a valid address and bus cycle defi-
							nition are present on the host bus. Some cache con-
							trollers perform more than one fetch in order to fill
							a cache line. In this case, the cache controller gen-
							erates HADS0# when it initiates the bus cycle for
							the first fetch. This triggers an state machine that
							generates HADS1# when it initiates any subse-
							quent bus cycles for the remaining fetches. Inter-
							nally, these two input signals are “anded” together.

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EISA System Architecture

Table1212- 6,- 6,contcont. .

HNA#	output	Host Next Address. In a system with a 386 host
		CPU, this output is used to tell the 386 whether it
		can output the address for the next bus cycle early.
HD/C#	input/output	Host Data or Control. Used as inputs when the
		host CPU is bus master, as outputs when a device
		other than the host CPU is bus master. In combina-
		tion with HW/R# and HM/IO#, defines the bus
		cycle type.
HW/R#	input/output	Host Write or Read. See HD/C#.
HM/IO#	input/output	Host Memory or I/O. See HD/C#.
HLOCK#	input	Host Lock. This input is connected to the host
		CPU's LOCK# output. Will be active when the host
		CPU is locking multiple bus cycles together to pre-
		vent other bus masters from requesting the buses
		until lock goes inactive.
HRDYI#	input	Host Ready Input. The host interface unit monitors
		this signal to determine when a host-initiated bus
		cycle has completed.
HRDYO#	output	Host Ready Output. When the host CPU is access-
		ing an EISA or ISA slave, the host interface unit
		activates HRDYO# to signal the end of the bus cy-
		cle to the host CPU.
HERDYO#	output	Host Early Ready Output. This is an earlier ver-
		sion of HRDYO# to be used with higher speed host
		CPUs that require more setup time.
HHOLD	output	Host Hold Request. When the Central Arbitration
		Control in the ISP chip must grant the buses to a
		device other than the host CPU, it must first take
		the buses away from the host CPU. To do this, the
		ISP activates DHOLD. DHOLD causes the EBC's
		host interface unit, in turn, to activate HHOLD to
		seize the host bus from the host CPU. In response,
		the host CPU surrenders the buses and activates
		HHLDA, Host Hold Acknowledge. The EBC then
		activates DHLDA to inform the Central Arbitration
		Control in the ISP that it may grant the buses to
		another device.
HHLDA	input	Host Hold Acknowledge. See HHOLD.

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Chapter 12: Intel 82350DT EISA Chipset

HLOCMEM#	input	Host Local Memory. This signal is set active by the
		memory address decode logic when memory resid-
		ing on the host bus is being addressed. If the cur-
		rent bus master is the host CPU, this means that the
		EBC does not have to activate the data EBB or run
		a bus cycle on the ISA or EISA bus.
HLOCIO#	input	Host Local I/O. This signal is set active by the I/O
		address decode logic when an I/O device residing
		on the host bus is being addressed. If the current
		bus master is the host CPU, this means that the
		EBC does not have to activate the data EBB or run
		a bus cycle on the ISA or EISA bus.
HGT16M#	input	Host Greater Than 16MB. This signal is only
		driven by the ISP chip during DMA bus cycles. If
		the DMA channel is generating a memory address
		below 16MB (00000000h – 00FFFFFFh), HGT16M#
		is high and the ISA interface unit will generate
		MRDC# or MWTC#. For addresses above 16MB,
		the MRDC# or MWTC# signals are not generated.
		This is necessary because some DMA devices use
		the ISA memory command signals to start a bus
		cycle early.
PWEN#	input	Posted Write Enable. If sampled active at the be-
		ginning of a host CPU memory write bus cycle to
		an EISA or ISA memory slave, the EBC's host inter-
		face unit causes the EBC's Data Buffer Control logic
		to latch the write data into the data EBB. The host
		interface unit then activates the HRDYO# signal to
		let the host CPU end the memory write bus cycle.
		The EBC's host interface unit, in conjunction with
		either the ISA or EISA interface unit, then writes
		the posted data to the target ISA or EISA memory
		slave. This feature allows single host memory
		writes to EISA or ISA memory to complete quickly.

175