Chapter 8: EISA DMA

Performance and Compatibility

Table 8-6 defines the data transfer rates when a DMA channel is programmed to use the Type B DMA bus cycle to transfer data.

Table 8-6. Type B Transfer Rates

	I/O Device Size			Transfer Rate
	8-bit			2.083MB/second
	16-bit			4.166MB/second
	32-bit			8.333MB/second

When a DMA channel is programmed to use the Type B DMA bus cycle to transfer data, the channel may be used to transfer data between fast, EISA memory and an I/O device designed for Type B transfers. In addition, some older, ISA I/O devices may also work with a channel programmed for Type B bus cycles. Although the Type B transfer involves a significant amount of compression compared to the ISA-compatible bus cycle, some ISA I/O devices may be fast enough to function correctly at this speed. Compatibility may be determined by testing.

Type C DMA Bus Cycle

Description

The Type C DMA bus cycle is very similar to the burst bus cycle run by a bursting EISA bus master or the main CPU. When the first bus cycle in a series is initiated, the DMA controller samples SLBURST# to determine if the addressed memory supports burst mode. In response to SLBURST# assertion, the controller then activates MSBURST# to indicate bursting will be used to transfer the data block. As with the other DMA bus cycle types, the controller uses the combination of DAKn# and either the IORC# or IOWC# line to address the I/O device. A byte, word or doubleword of data is transferred every BCLK cycle.

Performance and Compatibility

Table 8-7 defines the data transfer rates when a DMA channel is programmed to use the Type C DMA bus cycle to transfer data.

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