Chapter 11: Bridge, Translator, Pathfinder, Toolbox

Chapter 11

The Previous Chapter

The previous chapter introduced the buses around which all EISA systems are constructed. They are the host, EISA, ISA and X buses.

This Chapter

This chapter provides a description of the major functions performed by the EISA chipset. It acts as the bridge between the host and EISA buses. It translates addresses and other bus cycle information into a form understood by all of the host, EISA, ISA and X-bus devices in a system. When necessary, it performs data bus steering to ensure data travels over the correct paths between the current bus master and the currently-addressed device. It incorporates a toolbox including all of the standard support logic necessary in any EISA machine. It should be noted that the ISA bus is a subset of the EISA bus. For this reason, all references to the EISA bus in this or any other MindShare book refer to both the ISA bus and the Extended ISA bus (EISA).

The Next Chapter

The next chapter, “Intel 82350DT EISA Chipset,” provides an introduction to Intel's EISA chipset.

Bus Cycle Initiation

When a device requires the use of the bus to communicate with another device in the system, it requests the use of the bus from the CAC. Upon being granted ownership of the bus, the bus master initiates the bus cycle by addressing the target device, or slave.

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EISA System Architecture

Bridge

Upon sensing the start of the bus cycle, the EISA chipset must aid in the communication process. Acting as a bridge, the EISA chipset must allow the address generated by the bus master to propagate onto all of the system buses so all of the devices in the system have an opportunity to determine if they are currently being addressed. In this section, this function is referred to as bridging. This term isn't part of the EISA specification, but is employed here to reinforce the visual image of the process being described. Table 11-1 defines the circumstances under which the EISA chipset must act as a bridge. Figure 11-1 illustrates the relationship of the bridge to the three buses. At the start of a bus cycle, neither the current bus master nor the EISA chipset knows which bus the target slave is located on. For this reason, the EISA chipset always propagates addresses generated by the host CPU onto the EISA and X-buses. Conversely, it always propagates addresses by an EISA or ISA bus master onto the host and X-buses.

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Chapter 11: Bridge, Translator, Pathfinder, Toolbox

Table 11-1. Situations Requiring Address Bridging

	Bus Master Type			Slave Type			Action Required
	Host CPU			host slave			No bridging required.
	Host CPU			EISA slave			Address must be passed from the host
							bus to the EISA bus.
	Host CPU			ISA expansion			Address must be passed from the host
				slave			bus onto the ISA bus.
	Host CPU			ISA X-bus slave			Address must be passed from the host
							bus onto the ISA bus and then onto the X-
							bus.
	EISA Bus Master			host slave			Address must be passed from the EISA
							bus to the host bus.
	EISA Bus Master			EISA slave			No bridging required.
	EISA Bus Master			ISA expansion			No bridging required.
				slave
	EISA Bus Master			ISA X-bus slave			Address must be passed from the EISA
							bus to the X-bus.
	ISA Bus Master			host slave			Address must be passed from the ISA bus
							to the host bus.
	ISA Bus Master			EISA slave			No bridging required.
	ISA Bus Master			ISA expansion			No bridging required.
				slave
	ISA Bus Master			ISA X-bus slave			Address must be passed from the ISA bus
							to the X-bus.

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EISA System Architecture

Host Bus

}

Host Address Bus, HA2:HA31

Host Address Bus, HBE0#:HBE3#

Host Data Bus, HD0:HD31

EISA/Host		EISA/Host
Address Bridge		Data Bridge

EISA Bus

}

X-Bus

System Data Bus, SD0:SD31

System Address Bus

LA Bus

SBHE#

BE0#:BE3#

EISA/X-Bus	EISA/X-Bus
Address Buffer	Data
	Transceiver

X Address Bus

X Data Bus

XBHE#

Figure 11-1. The Bridge

In addition, under some circumstances the data being transferred between the bus master and the slave must be allowed to pass from one system bus to another. Table 11-2 defines these situations.

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Chapter 11: Bridge, Translator, Pathfinder, Toolbox

Table 11-2. Situations Requiring Data Bridging

	Bus Master
	Type			Slave Type			Action Required
	Host CPU			host slave			No bridging required.
	Host CPU			EISA slave			On a read, data must be passed from the EISA data
							bus to the host data bus. On a write, data must be
							passed from the host data bus to the EISA data bus.
	Host CPU			ISA expansion			On a read, data must be passed from the ISA data
				slave			bus to the host data bus. On a write, data must be
							passed from the host data bus to the ISA data bus.
	Host CPU			X-bus slave			On a read, data must be passed from the X data bus
							to the ISA data bus and then from the ISA data bus
							to the host data bus. On a write, data must be
							passed from the host data bus to the ISA data bus
							and then to the X data bus.
	EISA Bus			host slave			On a read, data must be passed from the host data
	Master						bus onto the EISA data bus. On a write, data must
							be passed from the EISA data bus to the host data
							bus.
	EISA Bus			EISA slave			No bridging required.
	Master
	EISA Bus			ISA expansion			No bridging required.
	Master			slave
	EISA Bus			X-bus slave			On a read, data must be passed from the X data bus
	Master						to the EISA data bus. On a write, data must be
							passed from the EISA data bus to the X data bus.
	ISA Bus			host slave			On a read, data must be passed from the host data
	Master						bus to the ISA data bus. On a write, data must be
							passed from the ISA data bus to the host data bus.
	ISA Bus			EISA slave			No bridging required.
	Master
	ISA Bus			ISA expansion			No bridging required.
	Master			slave
	ISA Bus			X-bus slave			On a read, data must be passed from the X data bus
	Master						to the ISA data bus. On a write, data must be passed
							from the ISA data bus to the X data bus.

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