- •Features
- •Pin Configurations
- •Disclaimer
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port B (PB5..PB0)
- •RESET
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •Atomic Byte Programming
- •Split Byte Programming
- •Erase
- •Write
- •I/O Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Default Clock Source
- •External Clock
- •System Clock Prescaler
- •Switching Time
- •Idle Mode
- •Power-down Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •Unconnected Pins
- •Alternate Port Functions
- •Alternate Functions of Port B
- •Register Description for I/O-Ports
- •Port B Data Register – PORTB
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Prescaler Reset
- •External Clock Source
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Operation
- •Starting a Conversion
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •debugWire Data Register – DWDR
- •Performing a Page Write
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Fuse Bytes
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Power-off sequence
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •ADC Characteristics – Preliminary Data
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Pin Pull-up
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Erratas
- •Table of Contents
ATtiny13
Avoid changing the calibration value in large steps when calibrating the calibrated internal RC Oscillator to ensure stable operation of the MCU. A variation in frequency of more than 2% from one cycle to the next can lead to unpredicatble behavior. Changes in OSCCAL should not exceed 0x20 for each calibration.
Table 6. Internal RC Oscillator Frequency Range
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Min Frequency in Percentage of |
Max Frequency in Percentage of |
OSCCAL Value |
Nominal Frequency |
Nominal Frequency |
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0x00 |
50% |
100% |
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0x3F |
75% |
150% |
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0x7F |
100% |
200% |
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External Clock |
To drive the device from an external clock source, CLKI should be driven as shown in |
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Figure 12. To run the device on an external clock, the CKSEL Fuses must be pro- |
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grammed to “00”. |
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Figure 12. External Clock Drive Configuration |
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EXTERNAL |
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CLKI |
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CLOCK |
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SIGNAL |
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GND |
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When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 7.
Table 7. Start-up Times for the External Clock Selection
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Start-up Time from Power- |
Additional Delay from |
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SUT1..0 |
down and Power-save |
Reset |
Recommended Usage |
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00 |
6 CK |
14CK |
BOD enabled |
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01 |
6 CK |
14CK + 4 ms |
Fast rising power |
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10 |
6 CK |
14CK + 64 ms |
Slowly rising power |
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11 |
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Reserved |
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When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page 24 for details.
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2535A–AVR–06/03