- •Features
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- •Timed Sequences for Changing the Configuration of the Watchdog Timer
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- •Safety Level 2
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- •Introduction
- •Configuring the Pin
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- •debugWIRE On-chip Debug System
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- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
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- •ADC Characteristics – Preliminary Data
- •Active Supply Current
- •Idle Supply Current
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- •Pin Pull-up
- •Register Summary
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- •Ordering Information
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- •Erratas
- •Table of Contents
ATtiny13
Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level.
Safety Level 1 |
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the |
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WDE bit to one without any restriction. A timed sequence is needed when disabling an |
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enabled Watchdog Timer. To disable an enabled Watchdog Timer, the following proce- |
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dure must be followed: |
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1. |
In the same operation, write a logic one to WDCE and WDE. A logic one must be |
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written to WDE regardless of the previous value of the WDE bit. |
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2. |
Within the next four clock cycles, in the same operation, write the WDE and WDP |
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bits as desired, but with the WDCE bit cleared. |
Safety Level 2 |
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read |
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as one. A timed sequence is needed when changing the Watchdog Time-out period. To |
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change the Watchdog Time-out, the following procedure must be followed: |
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1. |
In the same operation, write a logical one to WDCE and WDE. Even though the |
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WDE always is set, the WDE must be written to one to start the timed sequence. |
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2. |
Within the next four clock cycles, in the same operation, write the WDP bits as |
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desired, but with the WDCE bit cleared. The value written to the WDE bit is |
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irrelevant. |
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2535A–AVR–06/03