- •Features
- •Pin Configurations
- •Disclaimer
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port B (PB5..PB0)
- •RESET
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •Atomic Byte Programming
- •Split Byte Programming
- •Erase
- •Write
- •I/O Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Default Clock Source
- •External Clock
- •System Clock Prescaler
- •Switching Time
- •Idle Mode
- •Power-down Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •Unconnected Pins
- •Alternate Port Functions
- •Alternate Functions of Port B
- •Register Description for I/O-Ports
- •Port B Data Register – PORTB
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Prescaler Reset
- •External Clock Source
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Operation
- •Starting a Conversion
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •debugWire Data Register – DWDR
- •Performing a Page Write
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Fuse Bytes
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Power-off sequence
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •ADC Characteristics – Preliminary Data
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Pin Pull-up
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Erratas
- •Table of Contents
Fuse Bytes |
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The ATtiny13 has two Fuse bytes. Table 45 and Table 46 describe briefly the functional- |
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ity of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are |
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read as logical zero, “0”, if they are programmed. |
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Table 45. Fuse High Byte |
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Fuse High Byte |
Bit No |
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Description |
Default Value |
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– |
7 |
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1 (unprogrammed) |
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– |
6 |
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1 (unprogrammed) |
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– |
5 |
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– |
1 (unprogrammed) |
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SPMEN |
4 |
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SPM Enable |
1 (unprogrammed) |
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DWEN(3) |
3 |
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debugWire Enable |
1 (unprogrammed) |
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BODLEVEL1(1) |
2 |
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Brown-out Detector trigger level |
1 (unprogrammed) |
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BODLEVEL0(1) |
1 |
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Brown-out Detector trigger level |
1 (unprogrammed) |
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RSTDISBL(4) |
0 |
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External Reset disable |
1 (unprogrammed) |
Notes: 1. See Table 13 on page 32 for BODLEVEL Fuse decoding.
2.See “Alternate Functions of Port B” on page 48 for description of RSTDISBL and DWEN Fuses.
3.DWEN must be unprogrammed when Lock Bit security is required. See “Program And Data Memory Lock Bits” on page 99.
4.When programming the RSTDISBL Fuse, High-voltage Serial programming has to be used to change fuses to perform further programming.
Table 46. Fuse Low Byte
Fuse Low Byte |
Bit No |
Description |
Default Value |
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SPIEN(1) |
7 |
Enable Serial Program |
0 |
(programmed, SPI prog. |
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and Data Downloading |
enabled) |
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EEPROM memory is |
1 |
(unprogrammed, |
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EESAVE |
6 |
preserved through the |
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EEPROM not preserved) |
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Chip Erase |
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WDTON(2) |
5 |
Watchdog Timer always |
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on |
1 |
(unprogrammed) |
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CKDIV8(5) |
4 |
Divide clock by 8 |
0 |
(programmed) |
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SUT1 |
3 |
Select start-up time |
1 |
(unprogrammed)(3) |
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SUT0 |
2 |
Select start-up time |
0 |
(programmed)(3) |
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CKSEL1 |
1 |
Select Clock source |
1 |
(unprogrammed)(4) |
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CKSEL0 |
0 |
Select Clock source |
0 |
(programmed)(4) |
Notes: 1. The SPIEN Fuse is not accessible in SPI Programming mode.
2.See “Watchdog Timer Control Register – WDTCR” on page 35 for details.
3.The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 5 on page 22 for details.
4.The default setting of CKSEL1..0 results in internal RC Oscillator @ 9.6 MHz. See Table 4 on page 22 for details.
5.See “System Clock Prescaler” on page 24 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
100 ATtiny13
2535A–AVR–06/03