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Файл:AVR / datasheets / attiny_13.pdf
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- •Features
- •Pin Configurations
- •Disclaimer
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port B (PB5..PB0)
- •RESET
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •Atomic Byte Programming
- •Split Byte Programming
- •Erase
- •Write
- •I/O Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Default Clock Source
- •External Clock
- •System Clock Prescaler
- •Switching Time
- •Idle Mode
- •Power-down Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •Unconnected Pins
- •Alternate Port Functions
- •Alternate Functions of Port B
- •Register Description for I/O-Ports
- •Port B Data Register – PORTB
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Prescaler Reset
- •External Clock Source
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Operation
- •Starting a Conversion
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •debugWire Data Register – DWDR
- •Performing a Page Write
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Fuse Bytes
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Power-off sequence
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •ADC Characteristics – Preliminary Data
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Pin Pull-up
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Erratas
- •Table of Contents
Register Description for I/O-Ports
Port B Data Register – PORTB
Port B Data Direction Register
– DDRB
Port B Input Pins Address –
PINB
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Bit |
7 |
6 |
5 |
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4 |
3 |
2 |
1 |
0 |
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PORTB |
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– |
– |
PORTB5 |
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PORTB4 |
PORTB3 |
PORTB2 |
PORTB1 |
PORTB0 |
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Read/Write |
R |
R |
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R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
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Initial Value |
0 |
0 |
0 |
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0 |
0 |
0 |
0 |
0 |
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Bit |
7 |
6 |
5 |
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4 |
3 |
2 |
1 |
0 |
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DDRB |
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– |
– |
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DDB5 |
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DDB4 |
DDB3 |
DDB2 |
DDB1 |
DDB0 |
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Read/Write |
R |
R |
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R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
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Initial Value |
0 |
0 |
0 |
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0 |
0 |
0 |
0 |
0 |
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Bit |
7 |
6 |
5 |
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4 |
3 |
2 |
1 |
0 |
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– |
– |
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PINB5 |
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PINB4 |
PINB3 |
PINB2 |
PINB1 |
PINB0 |
PINB |
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Read/Write |
R |
R |
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R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
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Initial Value |
0 |
0 |
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N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
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50 ATtiny13
2535A–AVR–06/03
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