- •Features
- •Pin Configurations
- •Disclaimer
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port B (PB5..PB0)
- •RESET
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •Atomic Byte Programming
- •Split Byte Programming
- •Erase
- •Write
- •I/O Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Default Clock Source
- •External Clock
- •System Clock Prescaler
- •Switching Time
- •Idle Mode
- •Power-down Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •Unconnected Pins
- •Alternate Port Functions
- •Alternate Functions of Port B
- •Register Description for I/O-Ports
- •Port B Data Register – PORTB
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Prescaler Reset
- •External Clock Source
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Operation
- •Starting a Conversion
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •debugWire Data Register – DWDR
- •Performing a Page Write
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Fuse Bytes
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Power-off sequence
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •ADC Characteristics – Preliminary Data
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Pin Pull-up
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Erratas
- •Table of Contents
Electrical Characteristics
Absolute Maximum Ratings*
..................................Operating Temperature |
-55°C to +125°C |
*NOTICE: Stresses beyond those listed under “Absolute |
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Maximum Ratings” may cause permanent dam- |
Storage Temperature ..................................... |
-65°C to +150°C |
age to the device. This is a stress rating only and |
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functional operation of the device at these or |
Voltage on any Pin except |
RESET |
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other conditions beyond those indicated in the |
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with respect to Ground ................................ |
- 1.0V to VCC+0.5V |
operational sections of this specification is not |
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Voltage on |
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with respect to Ground |
-1.0V to +13.0V |
implied. Exposure to absolute maximum rating |
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RESET |
conditions for extended periods may affect |
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Maximum Operating Voltage |
6.0V |
device reliability. |
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DC Current per I/O Pin ............................................... |
40.0 mA |
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DC Current VCC and GND Pins................................ |
200.0 mA |
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DC Characteristics TA = -20°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)(1)
Symbol |
Parameter |
Condition |
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Min. |
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Typ. |
Max. |
Units |
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VIL |
Input Low Voltage |
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-0.5 |
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0.2VCC |
V |
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(3) |
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VIH |
Input High-voltage |
Except RESET pin |
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0.6VCC |
VCC +0.5 |
V |
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(3) |
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VIH2 |
Input High-voltage |
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RESET pin |
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0.9VCC |
VCC +0.5 |
V |
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VOL |
Output Low Voltage(4) |
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I |
OL |
= 10 mA, V |
CC |
= 5V |
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0.6 |
V |
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IOL = 5 mA, VCC = 3V |
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0.5 |
V |
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VOH |
Output High-voltage(5) |
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OH |
= -10 mA, V |
CC |
= 5V |
4.3 |
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V |
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(Port B) |
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IOH = -5 mA, VCC = 3V |
2.5 |
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V |
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IIL |
Input Leakage |
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Vcc = 5.5V, pin low |
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8 |
µA |
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Current I/O Pin |
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(absolute value) |
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IIH |
Input Leakage |
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Vcc = 5.5V, pin high |
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8 |
µA |
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Current I/O Pin |
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(absolute value) |
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RRST |
Reset Pull-up Resistor |
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20 |
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100 |
kΩ |
Rpu |
I/O Pin Pull-up Resistor |
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20 |
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100 |
kΩ |
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Active 1MHz, VCC = 2V |
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0.55 |
mA |
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Active 4MHz, VCC = 3V |
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3.5 |
mA |
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Power Supply Current |
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Active 8MHz, VCC = 5V |
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12 |
mA |
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ICC |
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Idle 1MHz, VCC = 2V |
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0.08 |
0.25 |
mA |
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Idle 4MHz, VCC = 3V |
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0.41 |
1.5 |
mA |
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Idle 8MHz, VCC = 5V |
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1.6 |
5.5 |
mA |
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Power-down mode |
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WDT enabled, VCC = 3V |
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< 5 |
16 |
µA |
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WDT disabled, VCC = 3V |
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< 0.5 |
8 |
µA |
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Notes: 1. All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual silicon.
2.“Max” means the highest value where the pin is guaranteed to be read as low.
3.“Min” means the lowest value where the pin is guaranteed to be read as high.
114 ATtiny13
2535A–AVR–06/03
ATtiny13
4.Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:
1] The sum of all IOL, for all ports, should not exceed 60 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.
5.Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:
1] The sum of all IOH, for all ports, should not exceed 60 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.
External Clock Drive Waveforms
Figure 60. External Clock Drive Waveforms
VIH1
VIL1
External Clock Drive
Table 58. External Clock Drive
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VCC = 1.8 - 5.5V |
VCC = 2.7 - 5.5V |
VCC = 4.5 - 5.5V |
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Symbol |
Parameter |
Min. |
Max. |
Min. |
Max. |
Min. |
Max. |
Units |
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1/tCLCL |
Clock Frequency |
0 |
TBD |
0 |
TBD |
0 |
TBD |
MHz |
tCLCL |
Clock Period |
TBD |
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TBD |
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TBD |
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ns |
tCHCX |
High Time |
TBD |
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TBD |
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TBD |
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ns |
tCLCX |
Low Time |
TBD |
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TBD |
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TBD |
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ns |
tCLCH |
Rise Time |
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TBD |
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TBD |
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TBD |
s |
tCHCL |
Fall Time |
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TBD |
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TBD |
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TBD |
s |
∆ tCLCL |
Change in period from one clock cycle to the next |
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2 |
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2 |
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2 |
% |
Figure 61. Maximum Frequency vs. VCC
16 MHz
9,6 MHz
Safe Operating
Area
2 MHz
1.8V |
2.7V |
4.5V |
5.5V |
115
2535A–AVR–06/03
ADC Characteristics – Preliminary Data
Table 59. |
ADC Characteristics |
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Symbol |
Parameter |
Condition |
Min |
Typ |
Max |
Units |
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Resolution |
Single Ended Conversion |
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10 |
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Bits |
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Differential Conversion |
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8 |
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Bits |
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Single Ended Conversion |
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VREF = 4V, VCC = 4V, |
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2 |
2.5 |
LSB |
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ADC clock = 200 kHz |
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Single Ended Conversion |
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VREF = 4V, VCC = 4V, |
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4.5 |
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LSB |
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Absolute accuracy (Including |
ADC clock = 1 MHz |
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Single Ended Conversion |
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INL, DNL, quantization error, |
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VREF = 4V, VCC = 4V, |
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gain and offset error) |
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2 |
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LSB |
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ADC clock = 200 kHz |
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Noise Reduction Mode |
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Single Ended Conversion |
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VREF = 4V, VCC = 4V, |
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4.5 |
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LSB |
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ADC clock = 1 MHz |
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Noise Reduction Mode |
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Single Ended Conversion |
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Integral Non-linearity (INL) |
VREF = 4V, VCC = 4V, |
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0.5 |
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LSB |
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ADC clock = 200 kHz |
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Single Ended Conversion |
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Differential Non-linearity (DNL) |
VREF = 4V, VCC = 4V, |
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0.25 |
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LSB |
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ADC clock = 200 kHz |
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Single Ended Conversion |
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Gain Error |
VREF = 4V, VCC = 4V, |
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LSB |
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ADC clock = 200 kHz |
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Single Ended Conversion |
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Offset Error |
VREF = 4V, VCC = 4V, |
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LSB |
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ADC clock = 200 kHz |
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Conversion Time |
Free Running Conversion |
13 |
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260 |
µs |
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Clock Frequency |
Single Ended Conversion |
50 |
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1000 |
kHz |
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AVCC |
Analog Supply Voltage |
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VCC - 0.3 |
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VCC + 0.3 |
V |
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VREF |
Reference Voltage |
Single Ended Conversion |
1.0 |
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AVCC |
V |
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Differential Conversion |
1.0 |
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AVCC - 0.5 |
V |
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VIN |
Input Voltage |
Single ended channels |
GND |
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VREF |
V |
Differential Conversion |
0 |
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AVCC(1) |
V |
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Input Bandwidth |
Single Ended Channels |
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38,5 |
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kHz |
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Differential Channels |
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4 |
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kHz |
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VINT |
Internal Voltage Reference |
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1.0 |
1.1 |
1.2 |
V |
RREF |
Reference Input Resistance |
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32 |
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kΩ |
RAIN |
Analog Input Resistance |
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100 |
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MΩ |
Note: 1. |
VDIFF must be below VREF |
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116 ATtiny13
2535A–AVR–06/03
ATtiny13
ATtiny13 Typical
Characteristics –
Preliminary Data
Active Supply Current
The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave.
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail- to-rail output is used as clock source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.
Figure 62. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
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0.1 - 1.0 MHz |
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2 |
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1.8 |
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5.5V |
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1.6 |
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5.0V |
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1.4 |
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4.5V |
(mA) |
1.2 |
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4.0V |
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1 |
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3.3V |
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CC |
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I |
0.8 |
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2.7V |
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0.6 |
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0.4 |
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1.8V |
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0.2 |
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0 |
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0 |
0.1 |
0.2 |
0.3 |
0.4 |
0.5 |
0.6 |
0.7 |
0.8 |
0.9 |
1 |
Frequency (MHz)
117
2535A–AVR–06/03
Figure 63. Active Supply Current vs. Frequency (1 - 16 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
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1 - 16 MHz |
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15 |
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5.5V |
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12.5 |
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5.0V |
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10 |
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4.5V |
(mA) |
7 |
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4.0V |
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CC |
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I |
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5 |
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3.3V |
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2.5 |
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2.7V |
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0 |
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1.8V |
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0 |
2 |
4 |
6 |
8 |
10 |
12 |
14 |
16 |
18 |
20 |
Frequency (MHz)
Figure 64. Active Supply Current vs. VCC (Internal RC Oscillator, 9.6 Mhz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 9.6 MHz
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12 |
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85°C |
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25°C |
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10 |
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-40°C |
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(mA) |
8 |
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CC |
6 |
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I |
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4 |
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2 |
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0 |
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1.5 |
2 |
2.5 |
3 |
3.5 |
4 |
4.5 |
5 |
5.5 |
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VCC (V) |
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118 ATtiny13
2535A–AVR–06/03