ATtiny25/45/85

8.1Internal Voltage Reference

ATtiny25/45/85 features an internal bandgap reference. This reference is used for Brown-out

Detection, and it can be used as an input to the Analog Comparator or the ADC.

8.1.1Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 8-4. To save power, the reference is not always turned on. The reference is on during the following situations:

1.When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).

2.When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).

3.When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.

	Table 8-4.	Internal Voltage Reference Characteristics(1)
	Symbol	Parameter	Condition	Min	Typ	Max	Units
	VBG	Bandgap reference voltage	VCC = 1.1V / 2.7V,	1.0	1.1	1.2	V
			TA = 25°C
	tBG	Bandgap reference start-up time	VCC = 2.7V,		40	70	µs
			TA = 25°C
	IBG	Bandgap reference current	VCC = 2.7V,		15		µA
		consumption	TA = 25°C
	Note: 1.	Values are guidelines only. Actual values are TBD.

8.2Watchdog Timer

The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 8-7 on page 44. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny25/45/85 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to Table 8-7 on page 44.

The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table 8-5. Refer to ”Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 45 for details.

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Table 8-5.
	WDT Configuration as a Function of the Fuse Settings of WDTON
		Safety	WDT Initial					How to Disable the	How to Change Time-
WDTON		Level	State					WDT	out
Unprogrammed		1	Disabled					Timed sequence	No limitations
Programmed		2	Enabled					Always enabled	Timed sequence

Figure 8-7. Watchdog Timer

128 kHz OSCILLATOR

WATCHDOG RESET

WDP0

WDP1

WDP2

WDP3

WDE

					WATCHDOG
					PRESCALER
OSC/2K			OSC/4K	OSC/8K	OSC/16K OSC/32K OSC/64K OSC/128K	OSC/256K		OSC/512K	OSC/1024K

MCU RESET

8.2.1Watchdog Timer Control Register – WDTCR

Bit	7	6	5	4	3	2	1	0
	WDIF	WDIE	WDP3	WDCE	WDE	WDP2	WDP1	WDP0	WDTCR
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	X	0	0	0

• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable

When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed instead of a reset if a timeout in the Watchdog Timer occurs.

If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared, the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt.

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ATtiny25/45/85

Table 8-6.	Watchdog Timer Configuration
WDE	WDIE	Watchdog Timer State	Action on Time-out
0	0	Stopped	None
0	1	Running	Interrupt
1	0	Running	Reset
1	1	Running	Interrupt

• Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This bit must also be set when changing the prescaler bits. See Section “8.3” on page 45.

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed:

1.In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts.

2.Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See Section “8.3” on page 45.

In safety level 1, WDE is overridden by WDRF in MCUSR. See ”MCU Status Register – MCUSR” on page 40 for description of WDRF. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.

Note:	If the watchdog timer is not going to be used in the application, it is important to go through a
	watchdog disable procedure in the initialization of the device. If the Watchdog is accidentally
	enabled, for example by a runaway pointer or brown-out condition, the device will be reset, which
	in turn will lead to a new watchdog reset. To avoid this situation, the application software should
	always clear the WDRF flag and the WDE control bit in the initialization routine.

• Bits 5, 2..0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 8-7.

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Table 8-7.
		Watchdog Timer Prescale Select
							Number of WDT Oscillator					Typical Time-out at
WDP3		WDP2	WDP1	WDP0						Cycles		VCC = 5.0V
0		0	0	0				2K		(2048) cycles		16 ms
0		0	0	1				4K		(4096) cycles		32 ms
0		0	1	0				8K		(8192) cycles		64 ms
0		0	1	1				16K		(16384) cycles		0.125 s
0		1	0	0				32K		(32764) cycles		0.25 s
0		1	0	1				64K		(65536) cycles		0.5 s
0		1	1	0				128K		(131072) cycles		1.0 s
0		1	1	1				256K		(262144) cycles		2.0 s
1		0	0	0				512K		(524288) cycles		4.0 s
1		0	0	1				1024K		(1048576) cycles		8.0 s
1		0	1	0
1		0	1	1
1		1	0	0						Reserved
1		1	0	1
1		1	1	0
1		1	1	1

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