ATtiny25/45/85

16. Dead Time Generator

The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be connected to Timer/Counter1 and it is used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary output pairs (OC1A-OC1A and OC1B-OC1B). The sharing of tasks is as follows: the timer/counter generates the PWM output and the Dead Time Generator generates the non-overlapping PWM output pair from the timer/counter PWM signal. Two Dead Time Generators are provided, one for each PWM output. The non-overlap time is adjustable and the PWM output and it’s complementary output are adjusted separately, and independently for both PWM outputs.

Figure 16-1. Timer/Counter1 & Dead Time Generators

PCKE

TIMER/COUNTER1

T15M

CK

PWM GENERATOR

PWM1A

PWM1B

PCK

DT1AH

DT1BH

DEAD TIME GENERATOR

DT1AL

DEAD TIME GENERATOR

DT1BL

OC1A

OC1B

OC1A

OC1B

The dead time generation is based on the 4-bit down counters that count the dead time, as shown in Figure 46. There is a dedicated prescaler in front of the Dead Time Generator that can divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8. This provides for large range of dead times that can be generated. The prescaler is controlled by two control bits DTPS11..10 from the I/O register at address 0x23. The block has also a rising and falling edge detector that is used to start the dead time counting period. Depending on the edge, one of the transitions on the rising edges, OC1x or OC1x is delayed until the counter has counted to zero. The comparator is used to compare the counter with zero and stop the dead time insertion when zero has been reached. The counter is loaded with a 4-bit DT1xH or DT1xL value from DT1x I/O register, depending on the edge of the PWM generator output when the dead time insertion is started.

Figure 16-2. Dead Time Generator

	T/C1 CLOCK DTPS11..10			COMPARATOR
				OC1x
	DEAD TIME	CLOCK CONTROL	4-BIT COUNTER
	PRESCALER
			DT1xH	OC1x
				DT1xL
				DT1x
				I/O REGISTER

PWM1x

The length of the counting period is user adjustable by selecting the dead time prescaler setting in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register

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consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM output and its’ complementary output separately. Thus the rising edge of OC1x and OC1x can have different dead time periods. The dead time is adjusted as the number of prescaled dead time generator clock cycles.

Figure 16-3. The Complementary Output Pair

PWM1x

OC1x

OC1x

x = A or B

t non-overlap / rising edge t non-overlap / falling edge

16.0.1Timer/Counter1 Dead Time Prescaler register 1 - DTPS1

Bit	7	6	5	4	3	2	1	0
$23 ($43)							DTPS11	DTPS10	DTPS1
Read/Write	R	R	R	R	R	R	R/W	R/W
Initial value	0	0	0	0	0	0	0	0

The dead time prescaler register, DTPS1 is a 2-bit read/write register.

The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can be generated. The Dead Time prescaler is controlled by two bits DTPS11..10 from the Dead Time Prescaler register. These bits define the division factor of the Dead Time prescaler. The division factors are given in table 46..

Table 16-1.	Division factors of the Dead Time prescaler
DTPS11		DTPS10	Prescaler divides the T/C1 clock by
0		0	1x (no division)
0		1	2x
1		0	4x
1		1	8x

16.0.2Timer/Counter1 Dead Time A - DT1A

Bit	7	6	5	4	3	2	1	0
$25 ($45)	DT1AH3	DT1AH2	DT1AH1	DT1AH0	DT1AL3	DT1AL2	DT1AL1	DT1AL0	DT1A
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial value	0	0	0	0	0	0	0	0

The dead time value register A is an 8-bit read/write register.

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The dead time delay of is adjusted by the dead time value register, DT1A. The register consists of two fields, DT1AH3..0 and DT1AL3..0, one for each complementary output. Therefore a different dead time delay can be adjusted for the rising edge of OC1A and the rising edge of OC1A.

• Bits 7..4- DT1AH3..DT1AH0: Dead Time Value for OC1A Output

The dead time value for the OC1A output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15.

• Bits 3..0- DT1AL3..DT1AL0: Dead Time Value for OC1A Output

The dead time value for the OC1A output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15.

16.0.3Timer/Counter1 Dead Time B - DT1B

Bit	7	6	5	4	3	2	1	0
$25 ($45)	DT1BH3	DT1BH2	DT1BH1	DT1BH0	DT1BL3	DT1BL2	DT1BL1	DT1BL0	DT1B
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial value	0	0	0	0	0	0	0	0

The dead time value register Bis an 8-bit read/write register.

The dead time delay of is adjusted by the dead time value register, DT1B. The register consists of two fields, DT1BH3..0 and DT1BL3..0, one for each complementary output. Therefore a different dead time delay can be adjusted for the rising edge of OC1A and the rising edge of OC1A.

• Bits 7..4- DT1BH3..DT1BH0: Dead Time Value for OC1B Output

The dead time value for the OC1B output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15.

• Bits 3..0- DT1BL3..DT1BL0: Dead Time Value for OC1B Output

The dead time value for the OC1B output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15.

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17. Universal Serial Interface – USI

The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load. The main features of the USI are:

•Two-wire Synchronous Data Transfer (Master or Slave, fSCLmax = fCK/16)

•Three-wire Synchronous Data Transfer (Master or Slave fSCKmax = fCK/4)

•Data Received Interrupt

•Wakeup from Idle Mode

•In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode

•Two-wire Start Condition Detector with Interrupt Capability

17.1Overview

A simplified block diagram of the USI is shown on Figure 17-1. For the actual placement of I/O pins, refer to ”Pinout ATtiny25/45/85” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the ”USI Register Descriptions” on page 117.

Figure 17-1. Universal Serial Interface, Block Diagram
									D Q	DO	(Output only)
									LE
	Bit7							Bit0		DI/SDA	(Input/Open Drain)
								3
					USIDR			2
								1	TIM0 COMP
								0
					USIDB
								3	0		(Input/Open Drain)
								2	1	USCK/SCL
BUSDATA	USISIF	USIOIF	USIPF	USIDC		4-bit Counter				Control Unit
					USISR			1
								0		CLOCK
										HOLD
									[1]	Two-wire Clock
						2
	USISIE	USIOIE	USIWM1	USIWM0	USICS1	USICS0	USICLK	USITC
					USICR

The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and outgoing data. The register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. The most significant bit is connected to one of two output pins depending of the wire mode configuration. A transparent latch is inserted between the Serial Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration.

The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate

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