- •Features
- •1. Pin Configurations
- •1.1 Disclaimer
- •2. Overview
- •2.1 Block Diagram
- •2.2 Pin Descriptions
- •2.2.3 Port B (PB5..PB0)
- •2.2.4 RESET
- •3. About Code Examples
- •4. AVR CPU Core
- •4.1 Introduction
- •4.2 Architectural Overview
- •4.4 Status Register
- •4.5 General Purpose Register File
- •4.6 Stack Pointer
- •4.7 Instruction Execution Timing
- •4.8 Reset and Interrupt Handling
- •4.8.1 Interrupt Response Time
- •5. AVR ATtiny25/45/85 Memories
- •5.2 SRAM Data Memory
- •5.2.1 Data Memory Access Times
- •5.3 EEPROM Data Memory
- •5.3.1 EEPROM Read/Write Access
- •5.3.5 Atomic Byte Programming
- •5.3.6 Split Byte Programming
- •5.3.7 Erase
- •5.3.8 Write
- •5.3.9 Preventing EEPROM Corruption
- •5.4 I/O Memory
- •6. System Clock and Clock Options
- •6.1 Clock Systems and their Distribution
- •6.2 Clock Sources
- •6.3 Default Clock Source
- •6.4 Crystal Oscillator
- •6.6 Calibrated Internal RC Oscillator
- •6.7 External Clock
- •6.8 128 kHz Internal Oscillator
- •6.9 Clock Output Buffer
- •6.10 System Clock Prescaler
- •6.10.2 Switching Time
- •7. Power Management and Sleep Modes
- •7.1 Idle Mode
- •7.2 ADC Noise Reduction Mode
- •7.4 Power Reduction Register
- •7.5 Minimizing Power Consumption
- •7.5.1 Analog to Digital Converter
- •7.5.2 Analog Comparator
- •7.5.4 Internal Voltage Reference
- •7.5.5 Watchdog Timer
- •7.5.6 Port Pins
- •8. System Control and Reset
- •8.0.1 Resetting the AVR
- •8.0.2 Reset Sources
- •8.0.3 Power-on Reset
- •8.0.4 External Reset
- •8.0.6 Watchdog Reset
- •8.1 Internal Voltage Reference
- •8.2 Watchdog Timer
- •8.3 Timed Sequences for Changing the Configuration of the Watchdog Timer
- •8.3.1 Safety Level 1
- •8.3.2 Safety Level 2
- •9. Interrupts
- •9.1 Interrupt Vectors in ATtiny25/45/85
- •10. External Interrupts
- •11. I/O Ports
- •11.1 Introduction
- •11.2 Ports as General Digital I/O
- •11.2.1 Configuring the Pin
- •11.2.2 Toggling the Pin
- •11.2.3 Switching Between Input and Output
- •11.2.4 Reading the Pin Value
- •11.2.5 Digital Input Enable and Sleep Modes
- •11.2.6 Unconnected Pins
- •11.3 Alternate Port Functions
- •11.3.2 Alternate Functions of Port B
- •12. 8-bit Timer/Counter0 with PWM
- •12.1 Overview
- •12.1.1 Registers
- •12.1.2 Definitions
- •12.2 Timer/Counter Clock Sources
- •12.3 Counter Unit
- •12.4 Output Compare Unit
- •12.4.1 Force Output Compare
- •12.4.2 Compare Match Blocking by TCNT0 Write
- •12.4.3 Using the Output Compare Unit
- •12.5 Compare Match Output Unit
- •12.5.1 Compare Output Mode and Waveform Generation
- •12.6 Modes of Operation
- •12.6.1 Normal Mode
- •12.6.2 Clear Timer on Compare Match (CTC) Mode
- •12.6.3 Fast PWM Mode
- •12.6.4 Phase Correct PWM Mode
- •12.7 Timer/Counter Timing Diagrams
- •13. Timer/Counter Prescaler
- •13.0.1 Prescaler Reset
- •13.0.2 External Clock Source
- •14. 8-bit Timer/Counter1
- •14.1 Timer/Counter1
- •14.1.1 Timer/Counter1 Control Register - TCCR1
- •14.1.2 General Timer/Counter1 Control Register - GTCCR
- •14.1.3 Timer/Counter1 - TCNT1
- •14.1.4 Timer/Counter1 Output Compare RegisterA - OCR1A
- •14.1.5 Timer/Counter1 Output Compare RegisterB - OCR1B
- •14.1.6 Timer/Counter1 Output Compare RegisterC - OCR1C
- •14.1.7 Timer/Counter Interrupt Mask Register - TIMSK
- •14.1.8 Timer/Counter Interrupt Flag Register - TIFR
- •14.1.9 PLL Control and Status Register - PLLCSR
- •14.1.10 Timer/Counter1 Initialization for Asynchronous Mode
- •14.1.11 Timer/Counter1 in PWM Mode
- •15. 8-bit Timer/Counter1 in ATtiny15 Mode
- •15.1 Timer/Counter1 Prescaler
- •15.2 Timer/Counter1
- •15.2.1 Timer/Counter1 Control Register - TCCR1
- •15.2.2 General Timer/Counter1 Control Register - GTCCR
- •15.2.3 Timer/Counter1 - TCNT1
- •15.2.4 Timer/Counter1 Output Compare RegisterA - OCR1A
- •15.2.5 Timer/Counter1 Output Compare Register C - OCR1C
- •15.2.6 Timer/Counter1 Interrupt Mask Register - TIMSK
- •15.2.7 Timer/Counter Interrupt Flag Register - TIFR
- •15.2.8 PLL Control and Status Register - PLLCSR
- •15.2.9 Timer/Counter1 in PWM Mode
- •16. Dead Time Generator
- •16.0.1 Timer/Counter1 Dead Time Prescaler register 1 - DTPS1
- •16.0.2 Timer/Counter1 Dead Time A - DT1A
- •16.0.3 Timer/Counter1 Dead Time B - DT1B
- •17.1 Overview
- •17.2 Functional Descriptions
- •17.2.2 SPI Master Operation Example
- •17.2.3 SPI Slave Operation Example
- •17.2.5 Start Condition Detector
- •17.3 Alternative USI Usage
- •17.3.4 Edge Triggered External Interrupt
- •17.3.5 Software Interrupt
- •17.4 USI Register Descriptions
- •18. Analog Comparator
- •18.1 Analog Comparator Multiplexed Input
- •19. Analog to Digital Converter
- •19.1 Features
- •19.2 Operation
- •19.3 Starting a Conversion
- •19.4 Prescaling and Conversion Timing
- •19.5 Changing Channel or Reference Selection
- •19.5.1 ADC Input Channels
- •19.5.2 ADC Voltage Reference
- •19.6 ADC Noise Canceler
- •19.6.1 Analog Input Circuitry
- •19.6.2 Analog Noise Canceling Techniques
- •19.6.3 ADC Accuracy Definitions
- •19.7 ADC Conversion Result
- •19.7.1 Single Ended Conversion
- •19.7.2 Unipolar Differential Conversion
- •19.7.3 Bipolar Differential Conversion
- •19.7.4 Temperature Measurement (Preliminary description)
- •19.7.7.1 ADLAR = 0
- •19.7.7.2 ADLAR = 1
- •20. debugWIRE On-chip Debug System
- •20.1 Features
- •20.2 Overview
- •20.3 Physical Interface
- •20.4 Software Break Points
- •20.5 Limitations of debugWIRE
- •20.6 debugWIRE Related Register in I/O Memory
- •21. Self-Programming the Flash
- •21.0.1 Performing Page Erase by SPM
- •21.0.2 Filling the Temporary Buffer (Page Loading)
- •21.0.3 Performing a Page Write
- •21.1.2 EEPROM Write Prevents Writing to SPMCSR
- •21.1.3 Reading the Fuse and Lock Bits from Software
- •21.1.4 Preventing Flash Corruption
- •21.1.5 Programming Time for Flash when Using SPM
- •22. Memory Programming
- •22.1 Program And Data Memory Lock Bits
- •22.2 Fuse Bytes
- •22.2.1 Latching of Fuses
- •22.3 Signature Bytes
- •22.3.1 ATtiny25 Signature Bytes
- •22.3.2 ATtiny45 Signature Bytes
- •22.3.3 ATtiny85 Signature Bytes
- •22.4 Calibration Byte
- •22.5 Page Size
- •22.6 Serial Downloading
- •22.6.1 Serial Programming Algorithm
- •22.6.2 Serial Programming Characteristics
- •22.7 High-voltage Serial Programming
- •22.8.2 Considerations for Efficient Programming
- •22.8.3 Chip Erase
- •22.8.4 Programming the Flash
- •22.8.5 Programming the EEPROM
- •22.8.6 Reading the Flash
- •22.8.7 Reading the EEPROM
- •22.8.8 Programming and Reading the Fuse and Lock Bits
- •22.8.9 Reading the Signature Bytes and Calibration Byte
- •23. Electrical Characteristics
- •23.1 Absolute Maximum Ratings*
- •23.2 External Clock Drive Waveforms
- •23.3 External Clock Drive
- •25. Register Summary
- •26. Instruction Set Summary
- •27. Ordering Information
- •27.1 ATtiny25
- •27.2 ATtiny45
- •27.3 ATtiny85
- •28. Packaging Information
- •29. Errata
- •29.1 ATtiny25/45/85 Rev. A
- •30. Datasheet Revision History
- •Table of Contents
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ATtiny25/45/85 |
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Select between increment and decrement. |
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Clear TCNT0 (set all bits to zero). |
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Timer/Counter clock, referred to as clkT0 in the following. |
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Signalize that TCNT0 has reached maximum value. |
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Signalize that TCNT0 has reached minimum value (zero). |
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC0A. For more details about advanced counting sequences and waveform generation, see ”Modes of Operation” on page 70.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
12.4Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See Section “12.6” on page 70.).
Figure 12-3 shows a block diagram of the Output Compare unit.
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2586A–AVR–02/05
Figure 12-3. Output Compare Unit, Block Diagram
DATA BUS
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TCNTn |
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= (8-bit Comparator ) |
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OCFnx (Int.Req.) |
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Waveform Generator |
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OCnx |
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WGMn1:0 COMnX1:0
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly.
12.4.1Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or toggled).
12.4.2Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled.
12.4.3Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform
68 ATtiny25/45/85
2586A–AVR–02/05