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14. 8-bit Timer/Counter1

The Timer/Counter1 is a general purpose 8-bit Timer/Counter module that has a separate prescaling selection from the separate prescaler.

Figure 14-1 shows the Timer/Counter1 prescaler that supports two clocking modes, a syncrhonous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base. The PCKE bit from the PLLCSR register enables the asynchronous mode when it is set (‘1’).

Figure 14-1. Timer/Counter1 Prescaler

PCKE	PSR1

CK

S T1CK PCK 64/32 MHz A

0

CS10

CS11

CS12

CS13

14-BIT

T/C PRESCALER

T1CK

T1CK/2

T1CK/4

T1CK/8

T1CK/16

T1CK/32

T1CK/64

T1CK/128

T1CK/256

T1CK/512

T1CK/1024

T1CK/2048

T1CK/4096

T1CK/8192

T1CK/16384

TIMER/COUNTER1 COUNT ENABLE

In the asynchronous clocking mode the clock selections are from PCK to PCK/16384 and stop, and in the synchronous clocking mode the clock selections are from CK to CK/16384 and stop. The clock options are described in Table 14-2 on page 88 and the Timer/Counter1 Control Register, TCCR1. Setting the PSR1 bit in GTCCR register resets the prescaler. The PCKE bit in the PLLCSR register enables the asynchronous mode. The frequency of the fast peripheral clock is 64 MHz (or 32 MHz in Low Speed Mode).

14.1Timer/Counter1

The Timer/Counter1 general operation is described in the asynchronous mode and the operation in the synchronous mode is mentioned only if there are differences between these two modes. Figure 14-2 shows Timer/Counter 1 synchronization register block diagram and synchronization delays in between registers. Note that all clock gating details are not shown in the figure. The Timer/Counter1 register values go through the internal synchronization registers, which cause the input synchronization delay, before affecting the counter operation. The registers TCCR1, GTCCR, OCR1A, OCR1B, and OCR1C can be read back right after writing the register. The read back values are delayed for the Timer/Counter1 (TCNT1) register and flags (OCF1A, OCF1B, and TOV1), because of the input and output synchronization.

The Timer/Counter1 features a high resolution and a high accuracy usage with the lower prescaling opportunities. It can also support two accurate, high speed, 8-bit Pulse Width Modulators using clock speeds up to 64 MHz ( or 32 MHz in Low Speed Mode). In this mode, Timer/Counter1 and the output compare registers serve as dual stand-alone PWMs with nonoverlapping non-inverted and inverted outputs. Refer to page 93 for a detailed description on

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this function. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions.

Figure 14-2. Timer/Counter 1 Synchronization Register Block Diagram.

8-BIT DATABUS

IO-registers

Input synchronization

Timer/Counter1

Output synchronization

registers

registers

OCR1A

OCR1A_SI

TCNT1

OCR1B

OCR1B_SI

TCNT_SO

OCR1C

OCR1C_SI

TCCR1

TCCR1_SI

OCF1A

OCF1A_SO

GTCCR

GTCCR_SI

TCNT1

TCNT1

TCNT1_SI

OCF1B

OCF1B_SO

OCF1A

OCF1A_SI

OCF1B

OCF1B_SI

TOV1

TOV1

TOV1_SI

TOV1_SO

PCKE

CK

S

PCK

A

S

A

SYNC

1/2 CK Delay

1 CK Delay

1/2 CK Delay

No Delay

MODE

ASYNC

~1/2 CK Delay

1 PCK Delay

1/2 PCK - 1 CK Delay

No Delay

MODE

Timer/Counter1 and the prescaler allow running the CPU from any clock source while the prescaler is operating on the fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock in the asynchronous mode.

Note that the system clock frequency must be lower than one third of the PCK frequency. The synchronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of the PCK when the system clock is high. If the frequency of the system clock is too high, it is a risk that data or control values are lost.

The following Figure 14-3 shows the block diagram for Timer/Counter1.

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Figure 14-3. Timer/Counter1 Block Diagram

T/C1 OVER- T/C1 COMPARE T/C1 COMPARE

OC1A

OC1B

OC1A

OC1B

FLOW IRQ MATCH A IRQ MATCH B IRQ

(PB1)

(PB0)

(PB4)

(PB3)

DEAD TIME GENERATOR

DEAD TIME GENERATOR

OCIE1A OCIE1B TOIE1 TOIE0	OCF1A OCF1B TOV1 TOV0
TIMER INT. MASK	TIMER INT. FLAG		T/C CONTROL	GLOBAL T/C CONTROL
REGISTER (TIMSK)	REGISTER (TIFR)	REGISTER 1 (TCCR1)		REGISTER (GTCCR)
	OCF1A OCF1B TOV1	CTC1	PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10	PWM1B COM1B1 COM1B0	FOC1B	FOC1A	PSR1
TIMER/COUNTER1
TIMER/COUNTER1	T/C CLEAR	T/C1 CONTROL					CK
(TCNT1)			LOGIC				PCK
8-BIT COMPARATOR	8-BIT COMPARATOR		8-BIT COMPARATOR
T/C1 OUTPUT	T/C1 OUTPUT		T/C1 OUTPUT
COMPARE REGISTER	COMPARE REGISTER		COMPARE REGISTER
(OCR1A)	(OCR1B)			(OCR1C)
8-BIT DATABUS

Three status flags (overflow and compare matches) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1 and GTCCR. The interrupt enable/disable settings are found in the Timer/Counter Interrupt Mask Register - TIMSK.

The Timer/Counter1 contains three Output Compare Registers, OCR1A, OCR1B, and OCR1C as the data source to be compared with the Timer/Counter1 contents. In normal mode the Output Compare functions are operational with all three output compare registers. OCR1A determines action on the OC1A pin (PB1), and it can generate Timer1 OC1A interrupt in normal mode and in PWM mode. Likewise, OCR1B determines action on the OC1B pin (PB3) and it can generate Timer1 OC1B interrupt in normal mode and in PWM mode. OCR1C holds the Timer/Counter maximum value, i.e. the clear on compare match value. In the normal mode an overflow interrupt (TOV1) is generated when Timer/Counter1 counts from $FF to $00, while in the PWM mode the overflow interrupt is generated when Timer/Counter1 counts either from $FF to $00 or from OCR1C to $00. The inverted PWM outputs OC1A and OC1B are not connected in normal mode.

In PWM mode, OCR1A and OCR1B provide the data values against which the Timer Counter value is compared. Upon compare match the PWM outputs (OC1A, OC1A, OC1B, OC1B) are generated. In PWM mode, the Timer Counter counts up to the value specified in the output compare register OCR1C and starts again from $00. This feature allows limiting the counter “full” value to a specified value, lower than $FF. Together with the many prescaler options, flexible PWM frequency selection is provided. Table 14-6 lists clock selection and OCR1C values to obtain PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution.

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14.1.1Timer/Counter1 Control Register - TCCR1

Bit	7	6	5	4	3	2	1	0
$30 ($50)	CTC1	PWM1A	COM1A1	COM1A0	CS13	CS12	CS11	CS10	TCCR1
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial value	0	0	0	0	0	0	0	0

• Bit 7- CTC1 : Clear Timer/Counter on Compare Match

When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match.

• Bit 6- PWM1A: Pulse Width Modulator A Enable

When set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.

• Bits 5,4 - COM1A1, COM1A0: Comparator A Output Mode, Bits 1 and 0

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1A is not connected in normal mode.

Table 14-1.	Comparator A Mode Select
COM1A1	COM1A0	Description
0	0	Timer/Counter Comparator A disconnected from output pin OC1A.
0	1	Toggle the OC1A output line.
1	0	Clear the OC1A output line.
1	1	Set the OC1A output line

In PWM mode, these bits have different functions. Refer to Table 14-4 on page 94 for a detailed description.

• Bits 3 .. 0 - CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

Table 14-2. Timer/Counter1 Prescale Select

				Asynchronous	Synchronous
CS13	CS12	CS11	CS10	Clocking Mode	Clocking Mode
0	0	0	0	T/C1 stopped	T/C1 stopped
0	0	0	1	PCK	CK
0	0	1	0	PCK/2	CK/2
0	0	1	1	PCK/4	CK/4
0	1	0	0	PCK/8	CK/8
0	1	0	1	PCK/16	CK/16
0	1	1	0	PCK/32	CK/32

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