- •Features
- •1. Pin Configurations
- •1.1 Disclaimer
- •2. Overview
- •2.1 Block Diagram
- •2.2 Pin Descriptions
- •2.2.3 Port B (PB5..PB0)
- •2.2.4 RESET
- •3. About Code Examples
- •4. AVR CPU Core
- •4.1 Introduction
- •4.2 Architectural Overview
- •4.4 Status Register
- •4.5 General Purpose Register File
- •4.6 Stack Pointer
- •4.7 Instruction Execution Timing
- •4.8 Reset and Interrupt Handling
- •4.8.1 Interrupt Response Time
- •5. AVR ATtiny25/45/85 Memories
- •5.2 SRAM Data Memory
- •5.2.1 Data Memory Access Times
- •5.3 EEPROM Data Memory
- •5.3.1 EEPROM Read/Write Access
- •5.3.5 Atomic Byte Programming
- •5.3.6 Split Byte Programming
- •5.3.7 Erase
- •5.3.8 Write
- •5.3.9 Preventing EEPROM Corruption
- •5.4 I/O Memory
- •6. System Clock and Clock Options
- •6.1 Clock Systems and their Distribution
- •6.2 Clock Sources
- •6.3 Default Clock Source
- •6.4 Crystal Oscillator
- •6.6 Calibrated Internal RC Oscillator
- •6.7 External Clock
- •6.8 128 kHz Internal Oscillator
- •6.9 Clock Output Buffer
- •6.10 System Clock Prescaler
- •6.10.2 Switching Time
- •7. Power Management and Sleep Modes
- •7.1 Idle Mode
- •7.2 ADC Noise Reduction Mode
- •7.4 Power Reduction Register
- •7.5 Minimizing Power Consumption
- •7.5.1 Analog to Digital Converter
- •7.5.2 Analog Comparator
- •7.5.4 Internal Voltage Reference
- •7.5.5 Watchdog Timer
- •7.5.6 Port Pins
- •8. System Control and Reset
- •8.0.1 Resetting the AVR
- •8.0.2 Reset Sources
- •8.0.3 Power-on Reset
- •8.0.4 External Reset
- •8.0.6 Watchdog Reset
- •8.1 Internal Voltage Reference
- •8.2 Watchdog Timer
- •8.3 Timed Sequences for Changing the Configuration of the Watchdog Timer
- •8.3.1 Safety Level 1
- •8.3.2 Safety Level 2
- •9. Interrupts
- •9.1 Interrupt Vectors in ATtiny25/45/85
- •10. External Interrupts
- •11. I/O Ports
- •11.1 Introduction
- •11.2 Ports as General Digital I/O
- •11.2.1 Configuring the Pin
- •11.2.2 Toggling the Pin
- •11.2.3 Switching Between Input and Output
- •11.2.4 Reading the Pin Value
- •11.2.5 Digital Input Enable and Sleep Modes
- •11.2.6 Unconnected Pins
- •11.3 Alternate Port Functions
- •11.3.2 Alternate Functions of Port B
- •12. 8-bit Timer/Counter0 with PWM
- •12.1 Overview
- •12.1.1 Registers
- •12.1.2 Definitions
- •12.2 Timer/Counter Clock Sources
- •12.3 Counter Unit
- •12.4 Output Compare Unit
- •12.4.1 Force Output Compare
- •12.4.2 Compare Match Blocking by TCNT0 Write
- •12.4.3 Using the Output Compare Unit
- •12.5 Compare Match Output Unit
- •12.5.1 Compare Output Mode and Waveform Generation
- •12.6 Modes of Operation
- •12.6.1 Normal Mode
- •12.6.2 Clear Timer on Compare Match (CTC) Mode
- •12.6.3 Fast PWM Mode
- •12.6.4 Phase Correct PWM Mode
- •12.7 Timer/Counter Timing Diagrams
- •13. Timer/Counter Prescaler
- •13.0.1 Prescaler Reset
- •13.0.2 External Clock Source
- •14. 8-bit Timer/Counter1
- •14.1 Timer/Counter1
- •14.1.1 Timer/Counter1 Control Register - TCCR1
- •14.1.2 General Timer/Counter1 Control Register - GTCCR
- •14.1.3 Timer/Counter1 - TCNT1
- •14.1.4 Timer/Counter1 Output Compare RegisterA - OCR1A
- •14.1.5 Timer/Counter1 Output Compare RegisterB - OCR1B
- •14.1.6 Timer/Counter1 Output Compare RegisterC - OCR1C
- •14.1.7 Timer/Counter Interrupt Mask Register - TIMSK
- •14.1.8 Timer/Counter Interrupt Flag Register - TIFR
- •14.1.9 PLL Control and Status Register - PLLCSR
- •14.1.10 Timer/Counter1 Initialization for Asynchronous Mode
- •14.1.11 Timer/Counter1 in PWM Mode
- •15. 8-bit Timer/Counter1 in ATtiny15 Mode
- •15.1 Timer/Counter1 Prescaler
- •15.2 Timer/Counter1
- •15.2.1 Timer/Counter1 Control Register - TCCR1
- •15.2.2 General Timer/Counter1 Control Register - GTCCR
- •15.2.3 Timer/Counter1 - TCNT1
- •15.2.4 Timer/Counter1 Output Compare RegisterA - OCR1A
- •15.2.5 Timer/Counter1 Output Compare Register C - OCR1C
- •15.2.6 Timer/Counter1 Interrupt Mask Register - TIMSK
- •15.2.7 Timer/Counter Interrupt Flag Register - TIFR
- •15.2.8 PLL Control and Status Register - PLLCSR
- •15.2.9 Timer/Counter1 in PWM Mode
- •16. Dead Time Generator
- •16.0.1 Timer/Counter1 Dead Time Prescaler register 1 - DTPS1
- •16.0.2 Timer/Counter1 Dead Time A - DT1A
- •16.0.3 Timer/Counter1 Dead Time B - DT1B
- •17.1 Overview
- •17.2 Functional Descriptions
- •17.2.2 SPI Master Operation Example
- •17.2.3 SPI Slave Operation Example
- •17.2.5 Start Condition Detector
- •17.3 Alternative USI Usage
- •17.3.4 Edge Triggered External Interrupt
- •17.3.5 Software Interrupt
- •17.4 USI Register Descriptions
- •18. Analog Comparator
- •18.1 Analog Comparator Multiplexed Input
- •19. Analog to Digital Converter
- •19.1 Features
- •19.2 Operation
- •19.3 Starting a Conversion
- •19.4 Prescaling and Conversion Timing
- •19.5 Changing Channel or Reference Selection
- •19.5.1 ADC Input Channels
- •19.5.2 ADC Voltage Reference
- •19.6 ADC Noise Canceler
- •19.6.1 Analog Input Circuitry
- •19.6.2 Analog Noise Canceling Techniques
- •19.6.3 ADC Accuracy Definitions
- •19.7 ADC Conversion Result
- •19.7.1 Single Ended Conversion
- •19.7.2 Unipolar Differential Conversion
- •19.7.3 Bipolar Differential Conversion
- •19.7.4 Temperature Measurement (Preliminary description)
- •19.7.7.1 ADLAR = 0
- •19.7.7.2 ADLAR = 1
- •20. debugWIRE On-chip Debug System
- •20.1 Features
- •20.2 Overview
- •20.3 Physical Interface
- •20.4 Software Break Points
- •20.5 Limitations of debugWIRE
- •20.6 debugWIRE Related Register in I/O Memory
- •21. Self-Programming the Flash
- •21.0.1 Performing Page Erase by SPM
- •21.0.2 Filling the Temporary Buffer (Page Loading)
- •21.0.3 Performing a Page Write
- •21.1.2 EEPROM Write Prevents Writing to SPMCSR
- •21.1.3 Reading the Fuse and Lock Bits from Software
- •21.1.4 Preventing Flash Corruption
- •21.1.5 Programming Time for Flash when Using SPM
- •22. Memory Programming
- •22.1 Program And Data Memory Lock Bits
- •22.2 Fuse Bytes
- •22.2.1 Latching of Fuses
- •22.3 Signature Bytes
- •22.3.1 ATtiny25 Signature Bytes
- •22.3.2 ATtiny45 Signature Bytes
- •22.3.3 ATtiny85 Signature Bytes
- •22.4 Calibration Byte
- •22.5 Page Size
- •22.6 Serial Downloading
- •22.6.1 Serial Programming Algorithm
- •22.6.2 Serial Programming Characteristics
- •22.7 High-voltage Serial Programming
- •22.8.2 Considerations for Efficient Programming
- •22.8.3 Chip Erase
- •22.8.4 Programming the Flash
- •22.8.5 Programming the EEPROM
- •22.8.6 Reading the Flash
- •22.8.7 Reading the EEPROM
- •22.8.8 Programming and Reading the Fuse and Lock Bits
- •22.8.9 Reading the Signature Bytes and Calibration Byte
- •23. Electrical Characteristics
- •23.1 Absolute Maximum Ratings*
- •23.2 External Clock Drive Waveforms
- •23.3 External Clock Drive
- •25. Register Summary
- •26. Instruction Set Summary
- •27. Ordering Information
- •27.1 ATtiny25
- •27.2 ATtiny45
- •27.3 ATtiny85
- •28. Packaging Information
- •29. Errata
- •29.1 ATtiny25/45/85 Rev. A
- •30. Datasheet Revision History
- •Table of Contents
ATtiny25/45/85
13. Timer/Counter Prescaler
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a
clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024.
13.0.1Prescaler Reset
The prescaler is free running, i.e., operates independently of the Clock Select logic of the Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution.
13.0.2External Clock Source
An external clock source applied to the T0 pin can be used as Timer/Counter clock (clkT0). The T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 13-1 shows a functional equivalent block diagram of the T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock.
The edge detector generates one clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects.
Figure 13-1. T0 Pin Sampling |
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Tn |
D |
Q |
D |
Q |
D |
Q |
Tn_sync |
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(To Clock |
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Select Logic) |
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LE |
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clkI/O |
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Synchronization |
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Edge Detector |
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
83
2586A–AVR–02/05
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 13-2. Prescaler for Timer/Counter0
clkI/O
Clear
PSR10
T0
Synchronization
clkT0
Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 13-1.
13.0.3General Timer/Counter Control Register – GTCCR
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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TSM |
PWM1B |
COM1B1 |
COM1B0 |
FOC1B |
FOC1A |
PSR1 |
PSR0 |
GTCCR |
Read/Write |
R/W |
R |
R |
R |
R |
R |
R |
R/W |
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Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR0 bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR0 bit is cleared by hardware, and the Timer/Counter start counting.
• Bit 0 – PSR0: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set.
84 ATtiny25/45/85
2586A–AVR–02/05