ATtiny25/45/85

2. Overview

The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2.1Block Diagram

Figure 2-1. Block Diagram

8-BIT DATABUS

				CALIBRATED
				INTERNAL
				OSCILLATOR
	PROGRAM	STACK	WATCHDOG	TIMING AND
	COUNTER	POINTER	TIMER	CONTROL
VCC
			MCU CONTROL
	PROGRAM	SRAM	REGISTER
	FLASH
			MCU STATUS
			REGISTER
GND	INSTRUCTION	GENERAL
	REGISTER	PURPOSE
		REGISTERS	TIMER/
		X	COUNTER0
	INSTRUCTION	Y
	DECODER	Z	TIMER/
			COUNTER1
	CONTROL	ALU	UNIVERSAL
			SERIAL
	LINES
			INTERFACE
		STATUS	INTERRUPT
			UNIT
		REGISTER
	PROGRAMMING		DATA	OSCILLATORS
	LOGIC		EEPROM
		DATA REGISTER	DATA DIR.	ADC /
		PORT B	REG.PORT B	ANALOG COMPARATOR
		PORT B DRIVERS
				RESET
		PB0-PB5

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

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2586A–AVR–02/05