4-2	Clocked Video Input Format Detection	UG-VIPSUITE
			2015.01.23

Output IP cores still accept data on the Avalon-ST Video interface for as long as there is space in the input FIFO.

The sequence for starting the output of the IP core:

1.Write a 1 to Control register bit 0.

2.Read Status register bit 0. When this bit is 1, the IP core produces data or video. This occurs on the next start of frame or field boundary.

Note: For CVI IP cores, the frame or field matches the Field order parameter settings.

The sequence for stopping the output of the IP core:

1.Write a 0 to Control register bit 0..

2.Read Status register bit 0. When this bit is 0, the IP core has stopped data output. This occurs on the next start of frame or field boundary

Note: For CVI IP cores, the frame or field matches the Field order parameter settings.

The starting and stopping of the IP core is synchronized to a frame or field boundary.

Table 4-2: Synchronization Settings for Clocked Video Input IP Cores

The table below lists the output of the CVI IP cores with the different Field order settings.

Video Format		Field Order		Output
Interlaced		F1 first		Start, F1, F0, ..., F1, F0, Stop
Interlaced		F0 first		Start, F0, F1, ..., F0, F1, Stop
Interlaced		Any field first		Start, F0 or F1, ... F0 or F1, Stop
Progressive		F1 first		No output
Progressive		F0 first		Start, F0, F0, ..., F0, F0, Stop
Progressive		Any field first		Start, F0, F0, ..., F0, F0, Stop

Clocked Video Input Format Detection

The CVI IP cores detect the format of the incoming clocked video and uses it to create the Avalon-ST Video control packet. The cores also provide this information in a set of registers.

Table 4-3: Format Detection

The CVI IP cores can detect different aspects of the incoming video stream.

Format			Description
Picture width (in samples)		•	The IP core counts the total number of samples per line,
			and the number of samples in the active picture period.
		•	One full line of video is required before the IP core can
			determine the width.

Altera Corporation	Clocked Video Interface IP Cores

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UG-VIPSUITE			Clocked Video Input Format Detection	4-3
2015.01.23
	Format		Description
	Picture height (in lines)		• The IP core counts the total number of lines per frame or
			field, and the number of lines in the active picture
			period.
			• One full frame or field of video is required before the IP
			core can determine the height.
	Interlaced/Progressive		• The IP core detects whether the incoming video is
			interlaced or progressive.
			• If it is interlaced, separate height values are stored for
			both fields.
			• One full frame or field of video and a line from a second
			frame or field are required before the IP core can
			determine whether the source is interlaced or progres
			sive.
	Standard		• The IP core provides the contents of the vid_std bus via
			the Standard register.
			• When connected to the rx_std signal of an SDI IP core,
			for example, these values can be used to report the
			standard (SD, HD, or 3G) of the incoming video.

Clocked Video Interface IP Cores	Altera Corporation

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	4-4	Clocked Video Input Format Detection	UG-VIPSUITE
			2015.01.23

•Clocked Video Input IP core

After reset, if the IP core has not yet determined the format of the incoming video, it uses the values specified under the Avalon-ST Video Initial/Default Control Packet section in the parameter editor. After determining an aspect of the incoming videos format, the IP core enters the value in the respective register, sets the registers valid bit in the Status register, and triggers the respective interrupts.

Table 4-4: Resolution Detection Sequence for a 1080i Incoming Video Stream

The table lists the sequence for a 1080i incoming video stream.

				Active		F0		F1		Total		F0		F1
		Interru				Active		Active				Total		Total
Status				Sample						Sample						Description
		pt				Line		Line				Sample		Sample
				Count		Count		Count		Count		Count		Count
00000000000		000		0		0		0		0		0		0		Start of incoming
																video.
00000001000		000		1,920		0		0		2,200		0		0		End of first line of
																video.
00100001000		100		1,920		0		0		2,200		0		0		Stable bit set and
																interrupt fired —
																Two of last three
																lines had the same
																sample count.
00100011000		100		1,920		540		0		2,200		563		0		End of first field of
																video.
00110011000		100		1,920		540		0		2,200		563		0		Interlaced bit set—
																Start of second field
																of video.
00111011000		100		1,920		540		540		2,200		563		562		End of second field
																of video.
10111011000		110		1,920		540		540		2,200		563		562		Resolution valid bit
																set and interrupt
																fired.

•Clocked Video Input II IP core

When the IP core detects a resolution, it uses the resolution to generate the Avalon-ST Video control

packets until a new resolution is detected. When the resolution valid bit in the Status register is 1, the

Active Sample Count, F0 Active Line Count, F1 Active Line Count, Total Sample Count, F0 Total Line Count, F1 Total Line Count, and Standard registers are valid and contain readable values. The interlaced bit of the Statusregister is also valid and can be read.

Altera Corporation	Clocked Video Interface IP Cores

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