UG-VIPSUITE	Control Synchronizer Signals	11-5
	2015.01.23

Control Synchronizer Signals

Table 11-2: Control Synchronizer Signals

	Signal		Directio		Description
			n
	clock		Input		The main system clock. The IP core operates on the
					rising edge of this signal.
	reset		Input		The IP core asynchronously resets when this signal is
					high. You must deassert this signal synchronously to the
					rising edge of the clock signal.
	din_data		Input		din port Avalon-ST data bus. This bus enables the
					transfer of pixel data into the IP core.
	din_endofpacket		Input		din port Avalon-ST endofpacket signal. This signal
					marks the end of an Avalon-ST packet.
	din_ready		Output		din port Avalon-ST ready signal. This signal indicates
					when the IP core is ready to receive data.
	din_startofpacket		Input		din port Avalon-ST startofpacket signal. This signal
					marks the start of an Avalon-ST packet.
	din_valid		Input		din port Avalon-ST valid signal. This signal identifies
					the cycles when the port must enter data.
	dout_data		Output		dout port Avalon-ST data bus. This bus enables the
					transfer of pixel data out of the IP core.
	dout_endofpacket		Output		dout port Avalon-ST endofpacket signal. This signal
					marks the end of an Avalon-ST packet.
	dout_ready		Input		dout port Avalon-ST ready signal. The downstream
					device asserts this signal when it is able to receive data.
	dout_startofpacket		Output		dout port Avalon-ST startofpacket signal. This signal
					marks the start of an Avalon-ST packet.
	dout_valid		Output		dout port Avalon-ST valid signal. The IP core asserts
					this signal when it produces data.
	slave_av_address		Input		slave port Avalon-MM address bus. This bus specifies a
					word offset into the slave address space.
	slave_av_read		Output		slave port Avalon-MM read signal. When you assert this
					signal, the slave port sends new data at readdata.
	slave_av_readdata		Output		slave port Avalon-MM readdata bus. The IP core uses
					these output lines for read transfers.
	slave_av_write		Input		slave port Avalon-MM write signal. When you assert
					this signal, the gamma_lut port accepts new data from the
					writedata bus.
Control Synchronizer IP Core						Altera Corporation
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	11-6		Control Synchronizer Control Registers				UG-VIPSUITE
						2015.01.23
			Signal		Directio		Description
					n
			slave_av_writedata		Input		slave port Avalon-MM writedata bus. The IP core uses
							these input lines for write transfers.
			status_update_int_w		Output		slave port Avalon-MM interrupt signal. Asserted to
							indicate that the interrupt registers of the IP core are
							updated; and the master must read them to determine
							what has occurred.
			master_av_address		Output		master port Avalon-MM address bus. This bus specifies
							a word offset into the Avalon-MM address space.
			master_av_writedata		Output		master port Avalon-MM writedata bus. The IP core
							uses these output lines for write transfers.
			master_av_write		Output		master port Avalon-MM write signal. Asserted to
							indicate write requests from the master to the system
							interconnect fabric.
			master_av_waitrequest		Input		master port Avalon-MM waitrequest signal. The
							system interconnect fabric asserts this signal to cause the
							master port to wait.

Control Synchronizer Control Registers

Table 11-3: Control Synchronizer Register Map

The control data is read once at the start of each frame and is buffered inside the IP core, so the registers can be safely updated during the processing of a frame.

Note: The width of each register of the frame reader is 32 bits.

Address		Register		Description
0		Control		• Bit 0 of this register is the Go bit. Setting this bit to 0 causes
				the IP core to start passing through data.
				• Bit 1 of this register is the interrupt enable. Setting this bit
				to 1 enables the completion of writes interrupt.
1		Status		Bit 0 of this register is the Status bit, all other bits are unused.
2		Interrupt		Bit 1 of this register is the completion of writes interrupt bit,
				all other bits are unused. Writing a 1 to bit 1 resets the
				completion of writes interrupt.

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UG-VIPSUITE					Control Synchronizer Control Registers	11-7
2015.01.23
	Address		Register		Description
	3		Disable Trigger		• Setting this register to 1 disables the trigger condition of
					the control synchronizer.
					• Setting this register to 0 enables the trigger condition of the
					control synchronizer.
					When you turn on the Require trigger reset via control port
					parameter, this register value is automatically set to 1 every
					time the control synchronizer triggers.
	4		Number of writes		This register sets how many write operations, starting with
					address and word 0, are written when the control synchron
					izer triggers.
	5		Address 0		Address where word 0 must be written on trigger condition.
6			Word 0		The word to write to address 0 on trigger condition.
	7		Address 1		Address where word 1 must be written on trigger condition.
8			Word 1		The word to write to address 1 on trigger condition.
	9		Address 2		Address where word 2 must be written on trigger condition.
10			Word 2		The word to write to address 2 on trigger condition.
	11		Address 3		Address where word 3 must be written on trigger condition.
12			Word 3		The word to write to address 3 on trigger condition.
	13		Address 4		Address where word 4 must be written on trigger condition.
14			Word 4		The word to write to address 4 on trigger condition.
	15		Address 5		Address where word 5 must be written on trigger condition.
16			Word 5		The word to write to address 5 on trigger condition.
	17		Address 6		Address where word 6 must be written on trigger condition.
18			Word 6		The word to write to address 6 on trigger condition.
	19		Address 7		Address where word 7 must be written on trigger condition.
20			Word 7		The word to write to address 7 on trigger condition.
	21		Address 8		Address where word 8 must be written on trigger condition.
22			Word 8		The word to write to address 8 on trigger condition.
	23		Address 9		Address where word 9 must be written on trigger condition.
24			Word 9		The word to write to address 9 on trigger condition.

Control Synchronizer IP Core	Altera Corporation

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