UG-VIPSUITE	Interrupts	4-5
	2015.01.23

Interrupts

The CVI IP cores produce a single interrupt line.

Table 4-5: Internal Interrupts

The table below lists the internal interrupts of the interrupt line.

IP Core		Internal Interrupts		Description
		Status update interrupt		Triggers when a change of resolution in the
				incoming video is detected.
		Stable video interrupt		• Triggers when the incoming video is
				detected as stable (has a consistent sample
Clocked Video Input IP core				length in two of the last three lines) or
				unstable (if, for example, the video cable is
				removed).
				• The incoming video is always detected as
				unstable when the vid_locked signal is
				low.
		Status update interrupt		Triggers when the stable bit, the vid locked
				bit or the resolution valid bit of the Status
				register changes value.
		End of field/frame		• If the synchronization settings are set to
		interrupt		Any field first, triggers on the falling edge
				of the v sync.
Clocked Video Input II IP core				• If the synchronization settings are set to
				F1 first, triggers on the falling edge of the
				F1 v sync.
				• If the synchronization settings are set to
				F0 first, you can use the interrupt to
				trigger the reading of the ancillary packets
				from the control interface before they are
				overwritten by the next frame.

These interrupts can be independently enabled using bits [2:1] of the Control register. Their values can be read using bits [2:1] of the Interrupt register. Writing 1 to either of these bits clears the respective interrupt.

Clocked Video Output Video Modes

The video frame is described using the mode registers that are accessed through the Avalon-MM control port.

If you turn off Use control port in the parameter editor for the CVO IP cores, then the output video format always has the format specified in the parameter editor.

Clocked Video Interface IP Cores	Altera Corporation

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	4-6	Clocked Video Output Video Modes	UG-VIPSUITE
			2015.01.23

The CVO IP cores can be configured to support between 1 to 14 different modes and each mode has a bank of registers that describe the output frame.

• Clocked Video Output IP Core

•When the IP core receives a new control packet on the Avalon-ST Video input, it searches the mode registers for a mode that is valid. The valid mode must have a field width and height that matches the width and height in the control packet.

• The Video Mode Match register shows the selected mode.

•If a matching mode is found, it restarts the video output with those format settings.

•If a matching mode is not found, the video output format is unchanged and a restart does not occur.

•Clocked Video Output II IP Core

•When the IP core receives a new control packet on the Avalon-ST Video input, it searches the mode registers for a mode that is valid. The valid mode must have a field width and height that matches the width and height in the control packet.

• The Video Mode Match register shows the selected mode.

•If a matching mode is found, it completes the current frame; duplicating data if needed before commencing output with the new settings at the beginning of the next frame.

•If a matching mode is not found, the video output format is unchanged.

Altera Corporation	Clocked Video Interface IP Cores

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	UG-VIPSUITE	Clocked Video Output Video Modes	4-7
	2015.01.23

Figure 4-1: Progressive Frame Parameters

The figure shows how the register values map to the progressive frame format.

Active picture line

F0 active picture

								V front
								porch
Ancillary line								V sync
								V back
								porch
	H front	H	H back		Active samples
	porch	sync	porch

H blanking

Active lines

V blanking

Clocked Video Interface IP Cores	Altera Corporation

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4-8 Clocked Video Output Video Modes

Figure 4-2: Interlaced Frame Parameters

The figure shows how the register values map to the interlaced frame format.

Active picture line

F0 active picture

F0 V rising
edge line			F0 V front
F rising			porch
edge line			F0 V sync
F0 ancillary line
			F0 V back
			porch

F1 active picture

								V front
F falling								porch
edge line								V sync
Ancillary line								V back
								porch
	H front	H	H back		Active samples
	porch	sync	porch

H blanking

UG-VIPSUITE 2015.01.23

F0 active lines

F0 V blank	Active lines
F1 active lines

V blanking

The mode registers can only be written to if a mode is marked as invalid.

Altera Corporation	Clocked Video Interface IP Cores

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