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2D FIR Filter Control Registers

5-5

2015.01.23

 

 

Signal

 

Direction

 

Description

 

 

 

 

 

din_ready

 

Output

 

din_N port Avalon-ST ready signal. The IP core asserts

 

 

 

 

this signal when it is able to receive data.

 

 

 

 

 

din_startofpacket

 

Input

 

din_N port Avalon-ST startofpacket signal. This signal

 

 

 

 

marks the start of an Avalon-ST packet.

din_valid

 

Input

 

din_N port Avalon-ST valid signal. This signal identifies

 

 

 

 

the cycles when the port must input data.

 

 

 

 

 

dout_data

 

Output

 

dout port Avalon-ST data bus. This bus enables the

 

 

 

 

transfer of pixel data out of the IP core.

dout_endofpacket

 

Output

 

dout_N port Avalon-ST endofpacket signal. This signal

 

 

 

 

marks the end of an Avalon-ST packet.

 

 

 

 

 

dout_ready

 

Input

 

dout_N port Avalon-ST ready signal. The downstream

 

 

 

 

device asserts this signal when it is able to receive data.

dout_startofpacket

 

Output

 

dout_N port Avalon-ST startofpacket signal. This signal

 

 

 

 

marks the start of an Avalon-ST packet.

 

 

 

 

 

dout_valid

 

Output

 

dout_N port Avalon-ST valid signal. The IP core asserts

 

 

 

 

this signal when it produces data.

 

 

 

 

 

2D FIR Filter Control Registers

Table 5-3: 2D FIR Filter Control Register Map

The width of each register in the 2D FIR Filter control register map is 32 bits. The coefficient registers use integer, signed 2’s complement numbers. To convert from fractional values, simply move the binary point right by the number of fractional bits specified in the parameter editor.

Note: The control data is read once at the start of each frame and is buffered inside the IP core, so the registers can be safely updated during the processing of a frame.

Address

 

Register

 

Description

 

 

 

 

 

0

 

Control

 

Bit 0 of this register is the Go bit, all other bits are unused.

 

 

 

 

Setting this bit to 0 causes the IP core to stop the next time

 

 

 

 

control information is read.

 

 

 

 

 

1

 

Status

 

Bit 0 of this register is the Status bit, all other bits are unused.

 

 

 

 

 

2

 

Coefficient 0

 

The coefficient at the top left (origin) of the filter kernel.

 

 

 

 

 

3

 

Coefficient 1

 

The coefficient at the origin across to the right by one.

 

 

 

 

 

4

 

Coefficient 2

 

The coefficient at the origin across to the right by two.

 

 

 

 

 

2D FIR Filter IP Core

Altera Corporation

 

 

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2D FIR Filter Control Registers

 

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2015.01.23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

Register

 

Description

 

 

 

 

 

 

 

 

 

n

Coefficient n

 

 

The coefficient at position:

Row (where 0 is the top row of the kernel) is the integer value through the truncation of (n–2) / (filter kernel width)

.

Column (where 0 is the far left row of the kernel) is the remainder of (n–2) / (filter kernel width).

Altera Corporation

2D FIR Filter IP Core

 

 

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