UG-VIPSUITE					Deinterlacing Signals	12-17
2015.01.23
	Parameter		Value		Description
	EDI read master FIFO depth		8–512, Default = 64		Select the FIFO depth of the edge-dependent
					interpolation (EDI) Avalon-MM read master
					interface.
	EDI read master FIFO burst		2–256, Default = 32		Select the burst target for EDI Avalon-MM
	target				read master interface.
	MA read master FIFO depth		8–512, Default = 64		Select the FIFO depth of the motion-adaptive
					(MA) Avalon-MM read master interface.
	MA read master FIFO burst		2–256, Default = 32		Select the burst target for MA Avalon-MM
	target				read master interface.
	Motion write master FIFO depth		8–512, Default = 64		Select the FIFO depth of the motion Avalon-
					MM write master interface.
	Motion write master FIFO burst		2–256, Default = 32		Select the burst target for the motion Avalon-
	target				MM write master interface.
	Motion read master FIFO depth		8–512, Default = 64		Select the FIFO depth of the motion Avalon-
					MM read master interface.
	Motion read master FIFO burst		2–256, Default = 32		Select the burst target for motion Avalon-
	target				MM read master interface.

Deinterlacing Signals

Table 12-4: Common Signals

These signals apply to all Deinterlacing IP cores.

		Signal		Directio		Description
				n
	•	clock (Deinterlacer)		Input		The main system clock. The IP core operates on the
	• av_st_clock (Deinterlacer II					rising edge of this signal.
		and Broadcast Deinterlacer)
	•	reset (Deinterlacer)		Input		The IP core asynchronously resets when this signal is
	• av_st_reset (Deinterlacer II					high. You must deassert this signal synchronously to the
						rising edge of the clock signal.
		and Broadcast Deinterlacer)
	din_data			Input		din port Avalon-ST data bus. This bus enables the
						transfer of pixel data into the IP core.
	din_endofpacket			Input		din port Avalon-ST endofpacket signal. This signal
						marks the end of an Avalon-ST packet.
	din_ready			Output		din port Avalon-ST ready signal. This signal indicates
						when the IP core is ready to receive data.
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		Signal		Directio		Description
				n
		din_startofpacket		Input		din port Avalon-ST startofpacket signal. This signal
						marks the start of an Avalon-ST packet.
		din_valid		Input		din port Avalon-ST valid signal. This signal identifies
						the cycles when the port must enter data.
		dout_data		Output		dout port Avalon-ST data bus. This bus enables the
						transfer of pixel data out of the IP core.
		dout_endofpacket		Output		dout port Avalon-ST endofpacket signal. This signal
						marks the end of an Avalon-ST packet.
		dout_ready		Input		dout port Avalon-ST ready signal. The downstream
						device asserts this signal when it is able to receive data.
		dout_startofpacket		Output		dout port Avalon-ST startofpacket signal. This signal
						marks the start of an Avalon-ST packet.
		dout_valid		Output		dout port Avalon-ST valid signal. The IP core asserts
						this signal when it produces data.
	Table 12-5: Signals for Deinterlacer IP Core
		Signal		Directio		Description
				n
		ker_writer_control_av_address		Input		ker_writer_control slave port Avalon-MM address
						bus. This bus specifies a word offset into the slave address
						space.
		ker_writer_control_av_		Input		ker_writer_control slave port Avalon-MM
		chipselect				chipselect signal. The ker_writer_control port
						ignores all other signals unless you assert this signal.
		ker_writer_control_av_readdata		Output		ker_writer_control slave port Avalon-MM readdata
						bus. The IP core uses these output lines for read
						transfers.
		ker_writer_control_av_		Output		ker_writer_control slave port Avalon-MM
		waitrequest				waitrequest signal.
		ker_writer_control_av_write		Input		ker_writer_control slave port Avalon-MM write
						signal. When you assert this signal, the ker_writer_
						control port accepts new data from the writedata bus.
		ker_writer_control_av_		Input		ker_writer_control slave port Avalon-MM
		writedata				writedata bus. The IP core uses these input lines for
						write transfers.
		ma_control_av_address		Input		ma_control slave port Avalon-MM address bus. This
						bus specifies a word offset into the slave address space.

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UG-VIPSUITE					Deinterlacing Signals	12-19
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	Signal		Directio		Description
			n
	ma_control_av_chipselect		Input		control slave port Avalon-MM chipselect signal. The
					ma_control port ignores all other signals unless you
					assert this signal.
	ma_control_av_readdata		Output		ma_control slave port Avalon-MM readdata bus. The
					IP core uses these output lines for read transfers.
	ma_control_av_waitrequest		Output		ma_control slave port Avalon-MM waitrequest signal.
	ma_control_av_write		Input		ma_control slave port Avalon-MM write signal. When
					you assert this signal, the ma_control port accepts new
					data from the writedata bus.
	ma_control_av_writedata		Input		ma_control slave port Avalon-MM writedata bus. The
					IP core uses these input lines for write transfers.
	read_master_N_av_address		Output		read_master_N port Avalon-MM address bus. This bus
					specifies a byte address in the Avalon-MM address space.
	read_master_N_av_burstcount		Output		read_master_N port Avalon-MM burstcount signal.
					This signal specifies the number of transfers in each
					burst.
	read_master_N_av_clock		Input		read_master_N port clock signal. The interface operates
					on the rising edge of the clock signal.
	read_master_N_av_read		Output		read_master_N port Avalon-MM read signal. The IP
					core asserts this signal to indicate read requests from the
					master to the system interconnect fabric.
	read_master_N_av_readdata		Input		read_master_N port Avalon-MM readdata bus. These
					input lines carry data for read transfers.
	read_master_N_av_readdatavalid		Input		read_master_N port Avalon-MM readdatavalid signal.
					The system interconnect fabric asserts this signal when
					the requested read data has arrived.
	read_master_N_av_reset		Input		read_master_N port reset signal. The interface asynchro
					nously resets when this signal is high. You must deassert
					this signal synchronously to the rising edge of the clock
					signal.
	read_master_N_av_waitrequest		Input		read_master_N port Avalon-MM waitrequest signal.
					The system interconnect fabric asserts this signal to cause
					the master port to wait.
	write_master_av_address		Output		write_master port Avalon-MM address bus. This bus
					specifies a byte address in the Avalon-MM address space.
	write_master_av_burstcount		Output		write_master port Avalon-MM burstcount signal. This
					signal specifies the number of transfers in each burst.

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		Signal		Directio		Description
				n
	write_master_av_clock			Input		write_master port clocksignal. The interface operates
						on the rising edge of the clock signal.
	write_master_av_reset			Input		write_master port reset signal. The interface
						asynchronously resets when this signal is high. You must
						deassert this signal synchronously to the rising edge of
						the clock signal.
	write_master_av_waitrequest			Input		write_master port Avalon-MM waitrequest signal.
						The system interconnect fabric asserts this signal to cause
						the master port to wait.
	write_master_av_write			Output		write_master port Avalon-MM write signal. The IP
						core asserts this signal to indicate write requests from the
						master to the system interconnect fabric.
	write_master_av_writedata			Output		write_master port Avalon-MM writedata bus. These
						output lines carry data for write transfers.
	Table 12-6: Signals for Deinterlacer II and Broadcast Deinterlacer IP Cores
		Signal		Directio		Description
				n
	av_mm_clock			Input		Clock for the Avalon-MM interfaces. The interfaces
						operate on the rising edge of this signal.
	av_mm_reset			Input		Reset for the Avalon-MM interfaces. The interfaces
						asynchronously reset when you assert this signal. You
						must deassert this signal synchronously to the rising edge
						of the av_mm_clock signal.
	control_address			Input		control slave port Avalon-MM address bus. This bus
						specifies a word offset into the slave address space.
	control_write			Input		controlslave port Avalon-MM write signal. When you
						assert this signal, the control port accepts new data from
						the writedata bus.
	control_writedata			Input		controlslave port Avalon-MM writedata bus. The IP
						core uses these input lines for write transfers.
	control_read			Output		control slave port Avalon-MM read signal. When you
						assert this signal, the control port produces new data at
						readdata.
	control_readdata			Output		control slave port Avalon-MM readdatavalid bus.
						The IP core uses these output lines for read transfers.
	control_readdatavalid			Output		control slave port Avalon-MM readdata bus. The IP
						core asserts this signal when the readdata bus contains
						valid data in response to the read signal.
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	Signal		Directio		Description
			n
	control_waitrequest		Output		control slave port Avalon-MM waitrequest signal.
	control_byteenable		Output		control slave port Avalon-MM byteenable bus. This
					bus enables specific byte lane or lanes during transfers.
					Each bit in byteenable corresponds to a byte in
					writedata and readdata.
					• During writes, byteenable specifies which bytes are
					being written to; the slave ignores other bytes.
					• During reads, byteenable indicates which bytes the
					master is reading. Slaves that simply return readdata
					with no side effects are free to ignore byteenable
					during reads.
	edi_read_master_address		Output		edi_read_master port Avalon-MM address bus. This
					bus specifies a byte address in the Avalon-MM address
					space.
	edi_read_master_read		Output		edi_read_master port Avalon-MM read signal. The IP
					core asserts this signal to indicate read requests from the
					master to the system interconnect fabric.
	edi_read_master_burstcount		Output		edi_read_master port Avalon-MM burstcount signal.
					This signal specifies the number of transfers in each
					burst.
	edi_read_master_readdata		Input		edi_read_master port Avalon-MM readdata bus.
					These input lines carry data for read transfers.
	edi_read_master_readdatavalid		Input		edi_read_master port Avalon-MM readdatavalid
					signal. The system interconnect fabric asserts this signal
					when the requested read data has arrived.
	edi_read_master_waitrequest		Input		edi_read_master port Avalon-MM waitrequest signal.
					The system interconnect fabric asserts this signal to cause
					the master port to wait.
	ma_read_master_address		Output		ma_read_master port Avalon-MM address bus. This
					bus specifies a byte address in the Avalon-MM address
					space.
	ma_read_master_read		Output		ma_read_master port Avalon-MM read signal. The IP
					core asserts this signal to indicate read requests from the
					master to the system interconnect fabric.
	ma_read_master_burstcount		Output		ma_read_master port Avalon-MM burstcount signal.
					This signal specifies the number of transfers in each
					burst.
	ma_read_master_readdata		Input		ma_read_master port Avalon-MM readdata bus. These
					input lines carry data for read transfers.
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Signal		Directio		Description
		n
ma_read_master_readdatavalid		Input		ma_read_master port Avalon-MM readdatavalid
				signal. The system interconnect fabric asserts this signal
				when the requested read data has arrived.
ma_read_master_waitrequest		Input		ma_read_master port Avalon-MM waitrequest signal.
				The system interconnect fabric asserts this signal to cause
				the master port to wait.
motion_read_master_address		Output		motion_read_master port Avalon-MM address bus.
				This bus specifies a byte address in the Avalon-MM
				address space.
motion_read_master_read		Output		motion_read_master port Avalon-MM read signal. The
				IP core asserts this signal to indicate read requests from
				the master to the system interconnect fabric.
motion_read_master_burstcount		Output		motion_read_master port Avalon-MM burstcount
				signal. This signal specifies the number of transfers in
				each burst.
motion_read_master_readdata		Input		motion_read_master port Avalon-MM readdata bus.
				These input lines carry data for read transfers.
motion_read_master_readdata-		Input		motion_read_master port Avalon-MM readdatavalid
valid				signal. The system interconnect fabric asserts this signal
				when the requested read data has arrived.
motion_read_master_waitrequest		Input		motion_read_master port Avalon-MM waitrequest
				signal. The system interconnect fabric asserts this signal
				to cause the master port to wait.
write_master_address		Output		write_master port Avalon-MM address bus. This bus
				specifies a byte address in the Avalon-MM address space.
write_master_write		Output		write_master port Avalon-MM write signal. The IP
				core asserts this signal to indicate write requests from the
				master to the system interconnect fabric.
write_master_burstcount		Output		write_master port Avalon-MM burstcount signal. This
				signal specifies the number of transfers in each burst.
write_master_writedata		Output		write_master port Avalon-MM writedata bus. These
				output lines carry data for write transfers.
write_master_waitrequest		Input		write_master port Avalon-MM waitrequest signal.
				The system interconnect fabric asserts this signal to cause
				the master port to wait.
motion_write_master_address		Output		motion_write_master port Avalon-MM address bus.
				This bus specifies a byte address in the Avalon-MM
				address space.

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