4-36		Clocked Video Interface Control Registers				UG-VIPSUITE
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			Signal		Direction		Description
			vid_trs		Output		Clocked video time reference signal (TRS) signal. Used
							with the SDI IP core to indicate a TRS, when asserted.
							Note: For embedded synchronization mode only.
			vid_v		Output		Clocked video vertical blanking signal. This signal is
							asserted during the vertical blanking period of the video
							stream.
							Note: For separate synchronization mode only.
			vid_v_sync		Output		Clocked video vertical synchronization signal. This signal
							is asserted during the vertical synchronization period of
							the video stream.
							Note: For separate synchronization mode only.

Clocked Video Interface Control Registers

Table 4-20: Clocked Video Input Registers

Address		Register		Description
0		Control		• Bit 0 of this register is the Go bit:
				• Setting this bit to 1 causes the CVI IP core start data
				output on the next video frame boundary.
				• Bits 3, 2, and 1 of the Control register are the interrupt
				enables:
				• Setting bit 1 to 1, enables the status update interrupt.
				• Setting bit 2 to 1, enables the stable video interrupt.
				• Setting bit 3 to 1, enables the synchronization outputs
				(sof, sof_locked, refclk_div).

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	Address		Register		Description
	1		Status		• Bit 0 of this register is the Status bit.
					• This bit is asserted when the CVI IP core is producing
					data.
					• Bits 5, 2, and 1 of the Status register are unused.
					• Bits 6, 4, and 3 are the resolution valid bits.
					• When bit 3 is asserted, the SampleCount register is
					valid.
					• When bit 4 is asserted, the F0LineCount register is
					valid.
					• When bit 6 is asserted, the F1LineCount register is
					valid.
					• Bit 7 is the interlaced bit:
					• When asserted, the input video stream is interlaced.
					• Bit 8 is the stable bit:
					• When asserted, the input video stream has had a
					consistent line length for two of the last three lines.
					• Bit 9 is the overflow sticky bit:
					• When asserted, the input FIFO has overflowed. The
					overflow sticky bit stays asserted until a 1 is written to
					this bit.
					• Bit 10 is the resolution bit:
					• When asserted, indicates a valid resolution in the
					sample and line count registers.
2			Interrupt		Bits 2 and 1 are the interrupt status bits:
					• When bit 1 is asserted, the status update interrupt has
					triggered.
					• When bit 2 is asserted, the stable video interrupt has
					triggered.
					• The interrupts stay asserted until a 1 is written to these
					bits.
	3		Used Words		The used words level of the input FIFO.
4			Active Sample Count		The detected sample count of the video streams excluding
					blanking.
	5		F0 Active Line Count		The detected line count of the video streams F0 field
					excluding blanking.
	6		F1 Active Line Count		The detected line count of the video streams F1 field
					excluding blanking.

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	4-38		Clocked Video Interface Control Registers				UG-VIPSUITE
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			Address		Register		Description
			7		Total Sample Count		The detected sample count of the video streams including
							blanking.
			8		F0 Total Line Count		The detected line count of the video streams F0 field including
							blanking.
			9		F1 Total Line Count		The detected line count of the video streams F1 field including
							blanking.
			10		Standard		The contents of the vid_std signal.
			11		SOF Sample		Start of frame line register. The line upon which the SOF
							occurs measured from the rising edge of the F0 vertical sync.
			12		SOF Line		SOF line register. The line upon which the SOF occurs
							measured from the rising edge of the F0 vertical sync.
			13		Refclk Divider		Number of cycles of vid_clk (refclk) before refclk_div
							signal triggers.
		Table 4-21: Clocked Video Input II Registers
			Address		Register		Description
			0		Control		• Bit 0 of this register is the Go bit:
							• Setting this bit to 1 causes the CVI II IP core to start
							data output on the next video frame boundary.
							• Bits 3, 2, and 1 of the Control register are the interrupt
							enables:
							• Setting bit 1 to 1, enables the status update interrupt.
							• Setting bit 2 to 1, enables the end of field/frame video
							interrupt.

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	Address		Register		Description
	1		Status		• Bit 0 of this register is the Status bit.
					• This bit is asserted when the CVI IP core is producing
					data.
					• Bits 6–1 of the Status register are unused.
					• Bit 7 is the interlaced bit:
					• When asserted, the input video stream is interlaced.
					• Bit 8 is the stable bit:
					• When asserted, the input video stream has had a
					consistent line length for two of the last three lines.
					• Bit 9 is the overflow sticky bit:
					• When asserted, the input FIFO has overflowed. The
					overflow sticky bit stays asserted until a 1 is written to
					this bit.
					• Bit 10 is the resolution bit:
					• When asserted, indicates a valid resolution in the
					sample and line count registers.
					• Bit 11 is the vid_locked bit:
					• When asserted, indicates current signal value of the
					vid_locked signal.
2			Interrupt		Bits 2 and 1 are the interrupt status bits:
					• When bit 1 is asserted, the status update interrupt has
					triggered.
					• When bit 2 is asserted, the end of field/frame interrupt has
					triggered.
					• The interrupts stay asserted until a 1 is written to these
					bits.
	3		Used Words		The used words level of the input FIFO.
4			Active Sample Count		The detected sample count of the video streams excluding
					blanking.
	5		F0 Active Line Count		The detected line count of the video streams F0 field
					excluding blanking.
	6		F1 Active Line Count		The detected line count of the video streams F1 field
					excluding blanking.
	7		Total Sample Count		The detected sample count of the video streams including
					blanking.
	8		F0 Total Line Count		The detected line count of the video streams F0 field including
					blanking.
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	4-40		Clocked Video Interface Control Registers				UG-VIPSUITE
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			Address		Register		Description
			9		F1 Total Line Count		The detected line count of the video streams F1 field including
							blanking.
			10		Standard		The contents of the vid_std signal.
			11		SOF Sample		Start of frame line register. The line upon which the SOF
							occurs measured from the rising edge of the F0 vertical sync.
			12		SOF Line		SOF line register. The line upon which the SOF occurs
							measured from the rising edge of the F0 vertical sync.
			13		Refclk Divider		Number of cycles of vid_clk (refclk) before refclk_div
							signal triggers.
			14		Reserved		Reserved for future use.
			15		Ancillary Packet		Start of the ancillary packets that have been extracted from the
							incoming video.
			15 + Depth of				End of the ancillary packets that have been extracted from the
			ancillary				incoming video.
			memory
		Table 4-22: Clocked Video Output Registers

The rows in the table are repeated in ascending order for each video mode. All of the ModeN registers are write only.

Address		Register		Description
0		Control		• Bit 0 of this register is the Go bit:
				• Setting this bit to 1 causes the CVO IP core start video
				data output.
				• Bits 3, 2, and 1 of the Control register are the interrupt
				enables:
				• Setting bit 1 to 1, enables the status update interrupt.
				• Setting bit 2 to 1, enables the locked interrupt.
				• Setting bit 3 to 1, enables the synchronization outputs
				(vid_sof, vid_sof_locked, vcoclk_div).
				• When bit 3 is set to 1, setting bit 4 to 1, enables frame
				locking. The CVO IP core attempts to align its vid_sof
				signal to the sof signal from the CVI IP core.

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UG-VIPSUITE					Clocked Video Interface Control Registers		4-41
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	Address		Register		Description
	1		Status		• Bit 0 of this register is the Status bit.
					• This bit is asserted when the CVO IP core is producing
					data.
					• Bit 1 of the Status register is unused.
					• Bit 2 is the underflow sticky bit.
					• When bit 2 is asserted, the output FIFO has
					underflowed. The underflow sticky bit stays asserted
					until a 1 is written to this bit.
					• Bit 3 is the frame locked bit.
					• When bit 3 is asserted, the CVO IP core has aligned its
					start of frame to the incoming sof signal.
2			Interrupt		Bits 2 and 1 are the interrupt status bits:
					• When bit 1 is asserted, the status update interrupt has
					triggered.
					• When bit 2 is asserted, the locked interrupt has triggered.
					• The interrupts stay asserted until a 1 is written to these
					bits.
	3		Used Words		The used words level of the output FIFO.
4			Video Mode Match		One-hot register that indicates the video mode that is selected.
	5		ModeX Control		Video Mode 1 Control.
					• Bit 0 of this register is the Interlaced bit:
					• Set to 1 for interlaced. Set to 0 for progressive.
					• Bit 1 of this register is the sequential output control bit
					(only if the Allow output of color planes in sequence
					compile-time parameter is enabled).
					• Setting bit 1 to 1, enables sequential output from the
					CVO IP core (NTSC). Setting bit 1 to a 0, enables
					parallel output from the CVO IP core (1080p).
6			Mode1 Sample Count		Video mode 1 sample count. Specifies the active picture width
					of the field.
	7		Mode1 F0 Line Count		Video mode 1 field 0/progressive line count. Specifies the
					active picture height of the field.
	8		Mode1 F1 Line Count		Video mode 1 field 1 line count (interlaced video only).
					Specifies the active picture height of the field.
	9		Mode1 Horizontal		Video mode 1 horizontal front porch. Specifies the length of
			Front Porch		the horizontal front porch in samples.
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			Address		Register		Description
			10		Mode1 Horizontal		Video mode 1 horizontal synchronization length. Specifies the
					Sync Length		length of the horizontal synchronization length in samples.
			11		Mode1 Horizontal		Video mode 1 horizontal blanking period. Specifies the length
					Blanking		of the horizontal blanking period in samples.
			12		Mode1 Vertical Front		Video mode 1 vertical front porch. Specifies the length of the
					Porch		vertical front porch in lines.
			13		Mode1 Vertical Sync		Video mode 1 vertical synchronization length. Specifies the
					Length		length of the vertical synchronization length in lines.
			14		Mode1 Vertical		Video mode 1 vertical blanking period. Specifies the length of
					Blanking		the vertical blanking period in lines.
			15		Mode1 F0 Vertical		Video mode 1 field 0 vertical front porch (interlaced video
					Front Porch		only). Specifies the length of the vertical front porch in lines.
			16		Mode1 F0 Vertical		Video mode 1 field 0 vertical synchronization length
					Sync Length		(interlaced video only). Specifies the length of the vertical
							synchronization length in lines.
			17		Mode1 F0 Vertical		Video mode 1 field 0 vertical blanking period (interlaced
					Blanking		video only). Specifies the length of the vertical blanking period
							in lines.
			18		Mode1 Active Picture		Video mode 1 active picture line. Specifies the line number
					Line		given to the first line of active picture.
			19		Mode1 F0 Vertical		Video mode 1 field 0 vertical blanking rising edge. Specifies
					Rising		the line number given to the start of field 0's vertical blanking.
			20		Mode1 Field Rising		Video mode 1 field rising edge. Specifies the line number
							given to the end of Field 0 and the start of Field 1.
			21		Mode1 Field Falling		Video mode 1 field falling edge. Specifies the line number
							given to the end of Field 0 and the start of Field 1.
			22		Mode1 Standard		The value output on the vid_std signal.
			23		Mode1 SOF Sample		Start of frame sample register. The sample and subsample
							upon which the SOF occurs (and the vid_sof signal triggers):
							• Bits 0–1 are the subsample value.
							• Bits 2–15 are the sample value.
			24		Mode1 SOF Line		SOF line register. The line upon which the SOF occurs
							measured from the rising edge of the F0 vertical sync.
			25		Mode1 Vcoclk Divider		Number of cycles of vid_clk (vcoclk) before vcoclk_div
							signal triggers.
			26		Mode1 Ancillary Line		The line to start inserting ancillary data packets.

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Address		Register		Description

27	Mode1 F0 Ancillary	The line in field F0 to start inserting ancillary data packets.
	Line
28	Mode1 Valid	Video mode 1 valid. Set to indicate that this mode is valid and
		can be used for video output.
29	ModeN Control ...	...

Table 4-23: Clocked Video Output II Registers

The rows in the table are repeated in ascending order for each video mode. All of the ModeN registers are write only.

Address		Register		Description
0		Control		• Bit 0 of this register is the Go bit:
				• Setting this bit to 1 causes the CVO IP core start video
				data output.
				• Bits 3, 2, and 1 of the Control register are the interrupt
				enables:
				• Setting bit 1 to 1, enables the status update interrupt.
				• Setting bit 2 to 1, enables the locked interrupt.
				• Setting bit 3 to 1, enables the synchronization outputs
				(vid_sof, vid_sof_locked, vcoclk_div).
				• When bit 3 is set to 1, setting bit 4 to 1, enables frame
				locking. The CVO IP core attempts to align its vid_sof
				signal to the sof signal from the CVI IP core.
1		Status		• Bit 0 of this register is the Status bit.
				• This bit is asserted when the CVO IP core is producing
				data.
				• Bit 1 of the Status register is unused.
				• Bit 2 is the underflow sticky bit.
				• When bit 2 is asserted, the output FIFO has
				underflowed. The underflow sticky bit stays asserted
				until a 1 is written to this bit.
				• Bit 3 is the frame locked bit.
				• When bit 3 is asserted, the CVO IP core has aligned its
				start of frame to the incoming sof signal.

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	4-44		Clocked Video Interface Control Registers				UG-VIPSUITE
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			Address		Register		Description
			2		Interrupt		Bits 2 and 1 are the interrupt status bits:
							• When bit 1 is asserted, the status update interrupt has
							triggered.
							• When bit 2 is asserted, the locked interrupt has triggered.
							• The interrupts stay asserted until a 1 is written to these
							bits.
			3		Video Mode Match		One-hot register that indicates the video mode that is selected.
			4		Bank Select		Selects which mode bank will be accessed by the proceeding
							writes. One-hot register with up to 16 banks available.
			5		ModeX Control		Video Mode 1 Control.
							• Bit 0 of this register is the Interlaced bit:
							• Set to 1 for interlaced. Set to 0 for progressive.
							• Bit 1 of this register is the sequential output control bit
							(only if the Allow output of color planes in sequence
							compile-time parameter is enabled).
							• Setting bit 1 to 1, enables sequential output from the
							CVO IP core (NTSC). Setting bit 1 to a 0, enables
							parallel output from the CVO IP core (1080p).
			6		Mode1 Sample Count		Video mode 1 sample count. Specifies the active picture width
							of the field.
			7		Mode1 F0 Line Count		Video mode 1 field 0/progressive line count. Specifies the
							active picture height of the field.
			8		Mode1 F1 Line Count		Video mode 1 field 1 line count (interlaced video only).
							Specifies the active picture height of the field.
			9		Mode1 Horizontal		Video mode 1 horizontal front porch. Specifies the length of
					Front Porch		the horizontal front porch in samples.
			10		Mode1 Horizontal		Video mode 1 horizontal synchronization length. Specifies the
					Sync Length		length of the horizontal synchronization length in samples.
			11		Mode1 Horizontal		Video mode 1 horizontal blanking period. Specifies the length
					Blanking		of the horizontal blanking period in samples.
			12		Mode1 Vertical Front		Video mode 1 vertical front porch. Specifies the length of the
					Porch		vertical front porch in lines.
			13		Mode1 Vertical Sync		Video mode 1 vertical synchronization length. Specifies the
					Length		length of the vertical synchronization length in lines.
			14		Mode1 Vertical		Video mode 1 vertical blanking period. Specifies the length of
					Blanking		the vertical blanking period in lines.

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	Address		Register		Description
	15		Mode1 F0 Vertical		Video mode 1 field 0 vertical front porch (interlaced video
			Front Porch		only). Specifies the length of the vertical front porch in lines.
	16		Mode1 F0 Vertical		Video mode 1 field 0 vertical synchronization length
			Sync Length		(interlaced video only). Specifies the length of the vertical
					synchronization length in lines.
	17		Mode1 F0 Vertical		Video mode 1 field 0 vertical blanking period (interlaced
			Blanking		video only). Specifies the length of the vertical blanking period
					in lines.
	18		Mode1 Active Picture		Video mode 1 active picture line. Specifies the line number
			Line		given to the first line of active picture.
	19		Mode1 F0 Vertical		Video mode 1 field 0 vertical blanking rising edge. Specifies
			Rising		the line number given to the start of field 0's vertical blanking.
	20		Mode1 Field Rising		Video mode 1 field rising edge. Specifies the line number
					given to the end of Field 0 and the start of Field 1.
	21		Mode1 Field Falling		Video mode 1 field falling edge. Specifies the line number
					given to the end of Field 0 and the start of Field 1.
	22		Mode1 Standard		The value output on the vid_std signal.
	23		Mode1 SOF Sample		Start of frame sample register. The sample and subsample
					upon which the SOF occurs (and the vid_sof signal triggers):
					• Bits 0–1 are the subsample value.
					• Bits 2–15 are the sample value.
24			Mode1 SOF Line		SOF line register. The line upon which the SOF occurs
					measured from the rising edge of the F0 vertical sync.
	25		Mode1 Vcoclk Divider		Number of cycles of vid_clk (vcoclk) before vcoclk_div
					signal triggers.
	26		Mode1 Ancillary Line		The line to start inserting ancillary data packets.
	27		Mode1 F0 Ancillary		The line in field F0 to start inserting ancillary data packets.
			Line
28			ModeN H-Sync		Specify positive or negative polarity for the horizontal sync.
			Polarity		• Bit 0 for falling edge pulses.
					• Bit 1 for rising edge hsync pulses.
	29		ModeN V-Sync		Specify positive or negative polarity for the vertical sync.
			Polarity		• Bit 0 for falling edge pulses.
					• Bit 1 for rising edge vsync pulses.
30			ModeN Valid		Video mode valid. Set to indicate that this mode is valid and
					can be used for video output.
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Note: For the Clocked Video Output IP cores, to ensure the vid_f signal rises at the Field 0 blanking period and falls at the Field 1, use the following equation:

F rising edge line > = Vertical blanking rising edge line

F rising edge line < Vertical blanking rising edge line + (Vertical sync +

Vertical front porch + Vertical back porch)

F falling edge line < active picture line

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