12-30		Design Guidelines for Broadcast Deinterlacer IP Core						UG-VIPSUITE
									2015.01.23
			Address		Register		RO/RW		Description
			25		Motion Shift		RW		Specifies the amount of raw motion (SAD) data that is
									right-shifted. Shifting is used to reduce sensitivity to
									noise when calculating motion (SAD) data for both
									bob and weave decisions and cadence detection.
									Note: It is very important to set this register
									correctly for good deinterlacing perform
									ance.
									Tune this register in conjunction with the motion
									visualization feature. Higher values decrease sensitivity
									to noise when calculating motion, but may start to
									introduce weave artefacts if the value used is too high.
									To improve video-over-film mode quality, consider
									using software to check the 3:2 Cadence State (VOF
									State) register, and to add one or two to the motion
									shift register's value when deinterlacing cadenced
									content.
									Range: 0–7
									Power on value: 4
			26		Visualize Film		RW		Specifies the film pixels in the current field to be
					Pixels				colored green for debugging purposes. Use this register
									in conjunction with the various VOF tuning registers.
									Range: 0–1
									Power on value: 0
			27		Visualize Motion		RW		Specifies the motion values for pixels represented with
					Values€				pink for debugging purposes. The greater the
									luminance of pink, the more motion is detected.
									Range: 0–1
									Power on value: 0

Design Guidelines for Broadcast Deinterlacer IP Core

The Broadcast Deinterlacer has a comprehensive set of CSR registers that allow precise tuning of the deinterlaced output. The exact register values used depend on the end system.

Altera Corporation	Deinterlacing IP Cores

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	UG-VIPSUITE	Design Guidelines for Broadcast Deinterlacer IP Core	12-31
	2015.01.23

Table 12-11: Suggested Register Settings For Altera UDX Reference Design

The table below shows the suggested register settings for Altera’s High-Definition Video (UDX) reference design with 10-bit YCbCr video.

Note: To ensure good quality, use these register settings after system reset. However, Altera recommends you to refine these settings, especially the motion shift register.

Register Address		Register		Suggested		Comments
(Decimal)				Settings
12		Cadence Detect On		1		• Set this register to 0 to disable
						cadence detection.
						• Set this register to 1 to enable 2:2,
						3:3,and video-over-film deinter
						lacing.
13		Video Threshold		65		For best results, adjust the video
						threshold based on the cadence state.
						Refer to Active Video Threshold
						Adjustment on page 1-32
16		VOF Lock Delay		14		—
17		Minimum Pixels		2000		For HD resolutions, try setting to
		Locked				10,000 instead.
18		Min Valid SAD Value		2		—
19		Scene Change		2		—
		Threshold/Bad Edit
		Detection
21		Minimum Pixel Kernel		230		—
		SAD for Field
		Repeats
22		History Minimum		5		—
		Value
23		History Maximum		7		—
		Value
24		SAD Mask		960		—
25		Motion Shift		5		Requires tuning. Refer to Tuning
						Motion Shift on page 1-32

Deinterlacing IP Cores	Altera Corporation

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	12-32	Design Guidelines for Broadcast Deinterlacer IP Core	UG-VIPSUITE
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Tuning Motion Shift

To tune the motion shift register, follow these steps:

1.Enable motion visualization; set Visualize Motion Values register to 1.

2.Disable cadence detection to ensure pure deinterlacing function is being observed; set Cadence Detect On register to 0.

3.Feed the Broadcast Deinterlacer IP core with the sequence of interest, ideally one with static areas and areas in motion, such as a waving flag sequence. Areas in the image where motion is detected will appear in pink, with the luminance in proportion to the amount of motion detected.

4.Adjust the Motion Shift register through software when the Broadcast Deinterlacer IP core runs, to observe the effect on the motion detected. Choose a motion shift value that does not cause any motion to be detected in static areas of the image.

Active Video Threshold Adjustment

For best video-over-film results, Altera recommends that the system processor performs the following steps:

•	Polls the 3:2 Cadence State (VOF State) register at least once per field.
•	Sets the Video Threshold register:
	•	to a high value, for instance 250, if the 3:2 Cadence State (VOF State) register is 0
	•	to a low value, for instance 1, if the 3:2 Cadence State (VOF State) register is 1

Altera Corporation	Deinterlacing IP Cores

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