Avalon-ST Video Monitor IP Core 21

2015.01.23

UG-VIPSUITE

Subscribe

Send Feedback

The Avalon-ST Video Monitor IP core is a debugging and monitoring component.

The Avalon-ST Video Monitor IP core together with the associated software in System Console captures and visualizes the flow of video data in a system. You can inspect the video data flow at multiple levels of abstraction from the Avalon-ST video protocol level down to raw packet data level.

The Avalon-ST Video Monitor IP core enables the visibility of the Avalon-ST video control and data packets streaming between video IP components. To monitor the video control and data packets, you must insert the monitor components into a system.

Figure 21-1: Avalon-ST Video Monitor Functional Block Diagram

The figure below shows the monitor components in a system.

Avalon-ST Sink

Avalon-ST Source

(din)

Avalon-ST Video Monitor

(dout)

Video IP

Video IP

Statistics and

Date Capture

Avalon-MM Slave	Avalon-ST Source
(control)	(capture)

Altera Trace System

The monitored Avalon-ST video stream enters the monitor through the din Avalon-ST sink port and leaves the monitor through the dout Avalon-ST source port. The monitor does not modify, delay, or stall the video stream in any way. Inside the monitor, the stream is tapped for you to gather statistics and sample data. The statistics and sampled data are then transmitted through the capture Avalon-ST source port to the trace system component. The trace system component then transmits the received information to the host. You may connect multiple monitors to the Trace System IP core.

© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO 9001:2008 Registered

www.altera.com

101 Innovation Drive, San Jose, CA 95134

	21-2	Packet Visualization	UG-VIPSUITE
			2015.01.23

Note: System Console uses the sopcinfo file (written by Qsys) or the .sof (written by the Quartus II software) to discover the connections between the trace system and the monitors. If you instantiate and manually connect the trace system and the monitors using HDL, System Console will not detect them.

Packet Visualization

System Console's Trace Table View contains a tabular view for displaying the information the monitors send out.

You can inspect the details of a video packet when you select a row in the trace table. The table offers the following detailed information:

•Statistics—Data flow statistics such as backpressure.

•Data—The sampled values for up to first 6 beats on the Avalon-ST data bus. [n] is the nth beat on the bus.

•Video control—Information about Avalon-ST video control packet.

•Video data—Packet size, the number of beats of the packet.

Note: When you turn the pixel capture feature, the packet displays a sub-sampled version of the real-time image packet in the video data section.

Table 21-1: Statistics

The table below lists the description of the available data flow statistics.

Statistics		Description
Data transfer cycles (beats)		The number of cycles transferring data.
Not ready and valid cycles (backpressure)		The number of cycles between start of packet and end of
		packet—the sink is not ready to receive data but the source
		has data to send.
Ready and not valid cycles (sink waiting)		The number of cycles between start of packet and end of
		packet—the sink is ready to receive data but the source has
		no data to send.
Not ready and not valid cycles		The number of cycles between start of packet and end of
		packet— the sink is not ready to receive data and the source
		has no data to send.
Inter packet valid cycles (backpressure)		The number of cycles before start of packet—the sink is not
		ready to receive data but the source has data to send.
Inter packet ready cycles		The number of cycles before start of packet—the sink is
		ready to receive data but the source has no data to send.
Backpressure		[(Not ready and valid cycles + Inter packet valid cycles) /
		(Data transfer cycles + Not ready and valid cycles + Ready
		and not valid cycles + Not ready and not valid cycles + Inter
		packet valid cycles)] × 100
		Note: Inter packet ready cycles are not included in the
		packet duration. A packet begins when a source
		is ready to send data.

Altera Corporation	Avalon-ST Video Monitor IP Core

Send Feedback

UG-VIPSUITE			Monitor Settings	21-3
2015.01.23
	Statistics		Description
	Utilization		[Data transfer cycles / (Data transfer cycles + Not ready and
			valid cycles + Ready and not valid cycles + Not ready and
			not valid cycles + Inter packet valid cycles)] × 100
			Note: Inter packet ready cycles are not included in the
			packet duration. A packet begins when a source
			is ready to send data.

Monitor Settings

The capture settings panel of the trace table provides convenient access to the monitor settings.

You can change the monitor settings with the trace_write_monitor and trace_read_monitor TCL commands. At the hardware level, you can access the register map through the control Avalon-MM slave port of the monitor component.

The capture settings panel offers three options.

•Enable—sends of statistics and sampled data.

•Disable—blocks the sending of statistics and sampled data.

•Enable with pixel capture— the monitor starts sampling the actual pixel data in the video data packets, and displays the captured pixels in the detailed event view.

The Capture Rate per 1000000 parameter controls the pixel percentage from randomly sampled data packets. A higher capture rate (closer to 1000000) displays a higher pixel percentage in the sample.

•If the capture rate is 5000 out of 1000000 pixels, the monitor attempts to sample one in every 200 pixels.

•If the monitor captures all the 1000000 pixels available, the monitor samples every pixel in the image.

•If there is not enough bandwidth to sample every pixel in the image, the reconstructed image may have a black and purple checkerboard pattern.

Assign a smaller capture rate value to allow the trace system to send all the debugging information through and avoid the checkerboard pattern.

Avalon-ST Video Monitor Parameter Settings

Table 21-2: Avalon-ST Video Monitor Parameter Settings

Parameter		Value		Description
Bits per pixel per color plane		4–20, Default = 8		Select the number of bits per pixel (per color
				plane).
Number of color planes in		1–3, Default = 3		Select the number of color planes sent in
parallel				parallel.

Avalon-ST Video Monitor IP Core	Altera Corporation

Send Feedback

21-4		Avalon-ST Video Monitor Signals					UG-VIPSUITE
						2015.01.23
		Parameter			Value		Description
		Number of color planes in		1–3, Default = 1			Select the number of color planes that are
		sequence					sent in sequence over one data connection.
							For example, a value of 3 for R'G'B' R'G'B'
							R'G'B'.
		Bit width of capture interface(s)		•	8		Select the data bus width of the Avalon-ST
				•	16		interface sending the captured information.
				•	32
				•	64
				•	128
		Capture video pixel data		On or Off			Turn on to enable the inclusion of hardware
							that allows the monitor to capture video data
							frames.

Avalon-ST Video Monitor Signals

Table 21-3: Avalon-ST Video Monitor Signals

Signal		Directio		Description
		n
clock_clk		Input		All signals on the monitor are synchronous to this clock.
				Drive this signal from the clock which drives the video
				components that are being monitored.
				Note: Do not insert clock crossing between the
				monitor and the trace system component.
				You must drive the trace system’s clock from
				the same source which drives this signal.
reset_reset		Input		This signal only resets the debugging parts of the
				monitor. It does not affect the system being monitored.
				Drive this signal directly from the reset_reset output
				of the trace system component.
din_data		Input		din port Avalon-ST data bus. This bus enables the
				transfer of pixel data into the IP core.
din_endofpacket		Input		din port Avalon-ST endofpacket signal. This signal
				marks the end of an Avalon-ST packet.
din_ready		Output		din port Avalon-ST ready signal. This signal indicates
				when the IP core is ready to receive data.
din_startofpacket		Input		din port Avalon-ST startofpacket signal. This signal
				marks the start of an Avalon-ST packet.

Altera Corporation	Avalon-ST Video Monitor IP Core

Send Feedback

UG-VIPSUITE					Avalon-ST Video Monitor Signals		21-5
2015.01.23
	Signal		Directio		Description
			n
	din_valid		Input		din port Avalon-ST valid signal. This signal identifies
					the cycles when the port must enter data.
	dout_data		Output		dout port Avalon-ST data bus. This bus enables the
					transfer of pixel data out of the IP core.
	dout_endofpacket		Output		dout port Avalon-ST endofpacket signal. This signal
					marks the end of an Avalon-ST packet.
	dout_ready		Input		dout port Avalon-ST ready signal. The downstream
					device asserts this signal when it is able to receive data.
	dout_startofpacket		Output		dout port Avalon-ST startofpacket signal. This signal
					marks the start of an Avalon-ST packet.
	dout_valid		Output		dout port Avalon-ST valid signal. The IP core asserts
					this signal when it produces data.
	capture_data		Output		capture port Avalon-ST data bus. This bus enables the
					transfer of data out of the IP core.
	capture_endofpacket		Output		capture port Avalon-ST endofpacket signal. This signal
					marks the end of an Avalon-ST packet.
	capture_empty		Output		capture port Avalon-ST empty signal.
	capture_ready		Input		capture port Avalon-ST ready signal. The downstream
					device asserts this signal when it is able to receive data.
	capture_startofpacket		Output		capture port Avalon-ST startofpacket signal. This
					signal marks the start of an Avalon-ST packet.
	capture_valid		Output		capture port Avalon-ST valid signal. The IP core
					asserts this signal when it produces data.
	control_address		Input		control slave port Avalon-MM address bus. This bus
					specifies a byte address in the Avalon-MM address space.
	control_burstcount		Input		control slave port Avalon-MM burstcount signal. This
					signal specifies the number of transfers in each burst.
	control_byteenable		Input		control slave port Avalon-MM byteenable bus.
	control_debugaccess		Input		control slave port Avalon-MM debugaccess signal.
	control_read		Input		control slave port Avalon-MM read signal. The IP core
					asserts this signal to indicate read requests from the
					master to the system interconnect fabric.
	controlreaddata		Output		control slave port Avalon-MM readdata bus. These
					input lines carry data for read transfers.
	control_readdatavalid		Output		control slave port Avalon-MM readdatavalid signal.
					The system interconnect fabric asserts this signal when
					the requested read data has arrived.
Avalon-ST Video Monitor IP Core						Altera Corporation
	Send Feedback