10-8		Color Space Conversion Signals					UG-VIPSUITE
							2015.01.23
		Parameter			Value		Description
					General
		Convert from signed to unsigned		•	Saturating to		Select the method of signed to unsigned
		by			minimum value at		conversion for the results.
					stage 4
				•	Replacing negative
					with absolute value
					Operands
		Run-time control		32–4096,			Turn on to enable run-time control of the
				Default = 1920			conversion values.
		Coefficient and summand		0–34, Default = 8			Specify the number of fraction bits for the
		fractional bits					fixed point type used to store the coefficients
							and summands.
		Coefficient precision: Signed		On or Off			Turn on to set the fixed point type used to
							store the constant coefficients as having a
							sign bit.
		Coefficient precision: Integer		0–16,			Specifies the number of integer bits for the
		bits		Default = 10			fixed point type used to store the constant
							coefficients.
		Summand precision: Signed		On or Off			Turn on to set the fixed point type used to
							store the constant summands as having a sign
							bit.
		Summand precision: Integer bits		0–22,			Specifies the number of integer bits for the
				Default = 10			fixed point type used to store the constant
							summands.

Color Space Conversion Signals

Table 10-3: Color Space Conversion Signals

The table below lists the signals for Color Space Converter and Color Space Converter II IP cores.

		Signal		Direction		Description
	reset			Input		The IP core asynchronously resets when you assert this
						signal. You must deassert this signal synchronously to the
						rising edge of the clock signal.
	clock			Input		The main system clock. The IP core operates on the rising
						edge of this signal.
	din_data			Input		din port Avalon-ST data bus. This bus enables the
						transfer of pixel data into the IP core.
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UG-VIPSUITE					Color Space Conversion Signals	10-9
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	Signal		Direction		Description
	din_endofpacket		Input		din port Avalon-ST endofpacket signal. This signal
					marks the end of an Avalon-ST packet.
	din_ready		Output		din port Avalon-ST ready signal. This signal indicates
					when the IP core is ready to receive data.
	din_startofpacket		Input		din port Avalon-ST startofpacket signal. This signal
					marks the start of an Avalon-ST packet.
	din_valid		Input		din port Avalon-ST valid signal. This signal identifies the
					cycles when the port must insert data.
	dout_data		Output		dout port Avalon-ST data bus. This bus enables the
					transfer of pixel data out of the IP core.
	dout_endofpacket		Output		dout port Avalon-ST endofpacket signal. This signal
					marks the end of an Avalon-ST packet.
	dout_ready		Input		dout port Avalon-ST ready signal. The downstream
					device asserts this signal when it is able to receive data.
	dout_startofpacket		Output		dout port Avalon-ST startofpacket signal. This signal
					marks the start of an Avalon-ST packet.
	dout_valid		Output		dout port Avalon-ST valid signal. The IP core asserts this
					signal when it produces data.
	control_address		Input		control slave port Avalon-MM address bus. This bus
					specifies a word offset into the slave address space.
	control_write		Input		controlslave port Avalon-MM write signal. When you
					assert this signal, the control port accepts new data from
					the writedata bus.
	control_writedata		Input		controlslave port Avalon-MM writedata bus. The IP
					core uses these input lines for write transfers.
	control_read		Output		control slave port Avalon-MM read signal. When you
					assert this signal, the control port produces new data at
					readdata.
	control_readdata		Output		control slave port Avalon-MM readdatavalid bus. The
					IP core uses these output lines for read transfers.
	control_readdatavalid		Output		control slave port Avalon-MM readdata bus. The IP
					core asserts this signal when the readdata bus contains
					valid data in response to the read signal.
	control_waitrequest		Output		control slave port Avalon-MM waitrequest signal.

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	10-10	Color Space Conversion Control Registers	UG-VIPSUITE
			2015.01.23

Signal		Direction		Description
control_byteenable		Output		control slave port Avalon-MM byteenable bus. This bus
				enables specific byte lane or lanes during transfers.
				Each bit in byteenable corresponds to a byte in
				writedata and readdata.
				• During writes, byteenable specifies which bytes are
				being written to; the slave ignores other bytes.
				• During reads, byteenable indicates which bytes the
				master is reading. Slaves that simply return readdata
				with no side effects are free to ignore byteenable
				during reads.

Color Space Conversion Control Registers

The width of each register in the Color Space Conversion control register map is 32 bits. To convert from fractional values, simply move the binary point right by the number of fractional bits specified in the user interface.

The control data is read once at the start of each frame and is buffered inside the IP cores, so the registers can be safely updated during the processing of a frame.

Table 10-4: Color Space Converter (CSC) Control Register

The table below describes the control register map for Color Space Converter IP core.

Address		Register		Description
0		Control		Bit 0 of this register is the Go bit, all other bits are unused.
				Setting this bit to 0 causes the IP core to stop the next time
				control information is read.
1		Status		Bit 0 of this register is the Status bit, all other bits are unused.

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	UG-VIPSUITE	Color Space Conversion Control Registers	10-11
	2015.01.23

Address		Register		Description

	2	Coefficient A0	The coefficient and summand registers use integer, signed 2’s
			complement numbers. Refer to Color Space Conversion on
	3	Coefficient B0
			page 10-2
	4	Coefficient C0
	5	Coefficient A1
	6	Coefficient B1
	7	Coefficient C1
	8	Coefficient A2
	9	Coefficient B2
	10	Coefficient C2
	11	Summand S0
	12	Summand S1
	13	Summand S2

Table 10-5: Color Space Converter II Control Register

The table below describes the control register map for Color Space Converter II IP core.

Address		Register		Description
0		Control		Bit 0 of this register is the Go bit, all other bits are unused.
				Setting this bit to 0 causes the IP core to stop the next time
				control information is read.
1		Status		Bit 0 of this register is the Status bit, all other bits are unused.
2		Interrupts		Bits 2 and 1 are the interrupt status bits:
				• When bit 1 is asserted, the status update interrupt has
				triggered.
				• When bit 2 is asserted, the stable video interrupt has
				triggered.
				• The interrupts stay asserted until a 1 is written to these
				bits.
3		Coeff-commit		Commit mode

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	10-12	Color Space Conversion Control Registers	UG-VIPSUITE
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Address		Register		Description

	4	Coefficient A0	The coefficient and summand registers use integer, signed 2’s
			complement numbers. Refer to Color Space Conversion on
	5	Coefficient B0
			page 10-2
	6	Coefficient C0
	7	Coefficient A1
	8	Coefficient B1
	9	Coefficient C1
	10	Coefficient A2
	11	Coefficient B2
	12	Coefficient C2
	13	Summand S0
	14	Summand S1
	15	Summand S2

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