UG-VIPSUITE					Video Mixing Signals	6-5
2015.01.23
	Parameter		Value		Description
	Run-time control		1		The Mixer II IP core always requires run-
					time control.

Video Mixing Signals

Table 6-3: Alpha Blending Mixer Signals

The table below lists the signals for Alpha Blending Mixer IP core.

	Signal		Direction		Description
	reset		Input		The IP core asynchronously resets when you assert this
					signal. You must deassert this signal synchronously to the
					rising edge of the clock signal.
	clock		Input		The main system clock. The IP core operates on the rising
					edge of this signal.
	control_av_address		Input		control slave port Avalon-MM address bus. This bus
					specifies a word offset into the slave address space.
	control_av_chipselect		Input		control slave port Avalon-MM chipselect signal. The
					control port ignores all other signals unless you assert
					this signal.
	control_av_readdata		Output		control slave port Avalon-MM readdata bus. The IP
					core uses these output lines for read transfers.
	control_av_write		Input		control slave port Avalon-MM write signal. When you
					assert this signal, the control port accepts new data from
					the writedata bus.
	control_av_writedata		Input		control slave port Avalon-MM writedata bus. The IP
					core uses these input lines for write transfers.
	din_N_data		Input		din_N port Avalon-ST data bus. This bus enables the
					transfer of pixel data into the IP core.
	din_N_endofpacket		Input		din_N port Avalon-ST endofpacket signal. This signal
					marks the end of an Avalon-ST packet.
	din_N_ready		Output		din_N port Avalon-ST ready signal. The IP core asserts
					this signal when it is able to receive data.
	din_N_startofpacket		Input		din_N port Avalon-ST startofpacket signal. This signal
					marks the start of an Avalon-ST packet.
	din_N_valid		Input		din_N port Avalon-ST valid signal. This signal identifies
					the cycles when the port must input data.
	dout_N_data		Output		dout port Avalon-ST data bus. This bus enables the
					transfer of pixel data out of the IP core.
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6-6		Video Mixing Signals				UG-VIPSUITE
					2015.01.23
		Signal		Direction		Description
		dout_N_endofpacket		Output		dout_N port Avalon-ST endofpacket signal. This signal
						marks the end of an Avalon-ST packet.
		dout_N_ready		Input		dout_N port Avalon-ST ready signal. The downstream
						device asserts this signal when it is able to receive data.
		dout_N_startofpacket		Output		dout_N port Avalon-ST startofpacket signal. This signal
						marks the start of an Avalon-ST packet.
		dout_N_valid		Output		dout_N port Avalon-ST valid signal. The IP core asserts
						this signal when it produces data.

Table 6-4: Alpha Signals for Alpha Blending Mixer IP Core

The table below lists the signals that are available only when you turn on Alpha blending in the Alpha Blending Mixer parameter editor. These signals that are available only for Alpha Blending Mixer IP core.

Signal		Direction		Description

alpha_in_N_data	Input	alpha_in_N port Avalon-ST data bus. This bus enables
		the transfer of pixel data into the IP core.
alpha_in_N_endofpacket	Input	alpha_in_N port Avalon-ST endofpacket signal. This
		signal marks the end of an Avalon-ST packet.
alpha_in_N_ready	Output	alpha_in_N port Avalon-ST ready signal. The IP core
		asserts this signal when it is able to receive data.
alpha_in_N_startofpacket	Input	alpha_in_N port Avalon-ST startofpacket signal. This
		signal marks the start of an Avalon-ST packet.
alpha_in_N_valid	Input	alpha_in_N port Avalon-ST valid signal. This signal
		identifies the cycles when the port must insert data.
Table 6-5: Mixer II Signals

The table below lists the signals for Mixer II IP core.

Signal		Direction		Description
reset		Input		The IP core asynchronously resets when you assert this
				signal. You must deassert this signal synchronously to the
				rising edge of the clock signal.
clock		Input		The main system clock. The IP core operates on the rising
				edge of this signal.
control_address		Input		control slave port Avalon-MM address bus. This bus
				specifies a word offset into the slave address space.
control_read		Output		control slave port Avalon-MM read signal. When you
				assert this signal, the control port produces new data at
				readdata.

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	UG-VIPSUITE	Video Mixing Signals	6-7
	2015.01.23

Signal		Direction		Description

control_readdata	Output	control slave port Avalon-MM readdata bus. The IP
		core uses these output lines for read transfers.
control_readdatavalid	Output	control slave port Avalon-MM readdata bus. The IP
		core asserts this signal when the readdata bus contains
		valid data in response to the read signal.
control_write	Input	control slave port Avalon-MM write signal. When you
		assert this signal, the control port accepts new data from
		the writedata bus.
control_writedata	Input	control slave port Avalon-MM writedata bus. The IP
		core uses these input lines for write transfers.
control_waitrequest	Output	control slave port Avalon-MM waitrequest signal.
control_byteenable	Output	control slave port Avalon-MM byteenable bus. This bus
		enables specific byte lane or lanes during transfers.
		Each bit in byteenable corresponds to a byte in
		writedata and readdata.
		• During writes, byteenable specifies which bytes are
		being written to; the slave ignores other bytes.
		• During reads, byteenable indicates which bytes the
		master is reading. Slaves that simply return readdata
		with no side effects are free to ignore byteenable
		during reads.
din_N_data	Input	din_N port Avalon-ST data bus. This bus enables the
		transfer of pixel data into the IP core.
din_N_endofpacket	Input	din_N port Avalon-ST endofpacket signal. This signal
		marks the end of an Avalon-ST packet.
din_N_ready	Output	din_N port Avalon-ST ready signal. The IP core asserts
		this signal when it is able to receive data.
din_N_startofpacket	Input	din_N port Avalon-ST startofpacket signal. This signal
		marks the start of an Avalon-ST packet.
din_N_valid	Input	din_N port Avalon-ST valid signal. This signal identifies
		the cycles when the port must input data.
dout_N_data	Output	dout port Avalon-ST data bus. This bus enables the
		transfer of pixel data out of the IP core.
dout_N_endofpacket	Output	dout_N port Avalon-ST endofpacket signal. This signal
		marks the end of an Avalon-ST packet.
dout_N_ready	Input	dout_N port Avalon-ST ready signal. The downstream
		device asserts this signal when it is able to receive data.

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	6-8	Video Mixing Control Registers	UG-VIPSUITE
			2015.01.23

Signal		Direction		Description
dout_N_startofpacket		Output		dout_N port Avalon-ST startofpacket signal. This signal
				marks the start of an Avalon-ST packet.
dout_N_valid		Output		dout_N port Avalon-ST valid signal. The IP core asserts
				this signal when it produces data.

Video Mixing Control Registers

For efficiency reasons, the Video and Image Processing Suite IP cores buffer a few samples from the input stream even if they are not immediately processed. This implies that the Avalon-ST inputs for foreground layers assert ready high, and buffer a few samples even if the corresponding layer has been deactivated.

Table 6-6: Alpha Blending Mixer Control Register Map

The table below describes the control register map for Alpha Blending Mixer IP core.

Address		Register		Description
0		Control		Bit 0 of this register is the Go bit, all other bits are unused.
				Setting this bit to 0 causes the IP core to stop the next time
				control information is read.
1		Status		Bit 0 of this register is the Status bit, all other bits are unused.
2		Layer 1 X		Offset in pixels from the left edge of the background layer to
				the left edge of layer 1.
3		Layer 1 Y		Offset in pixels from the top edge of the background layer to
				the top edge of layer 1.
4		Layer 1 Active		• If set to 0—data from the input stream is not pulled out.
				• If set to 1—layer 1 is displayed.
				• If set to 2—data in the input stream is consumed but not
				displayed. The IP core still propagates the Avalon-ST
				packets of type 2 to 14 as usual.
				The value of this register is checked at the start of each frame.
				If the register is changed during the processing of a video
				frame, the change does not take effect until the start of the
				next frame.
5		Layer 2 X		The rows in the table are repeated in ascending order for each
				layer from 1 to the foreground layer...

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	UG-VIPSUITE	Video Mixing Control Registers	6-9
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Table 6-7: Mixer II Control Register Map

The table below describes the control register map for Mixer II IP core.

Address		Register		Description

0		Control		Bit 0 of this register is the Go bit, all other bits are unused.
				Setting this bit to 0 causes the IP core to stop the next time
				control information is read.
	1	Status		Bit 0 of this register is the Status bit, all other bits are unused.
2		Interrupt		Unused.
	3	Input 0	X	X offset in pixels from the left edge of the background layer to
				the left edge of input 0.
	4	Input 0	Y	Y offset in pixels from the top edge of the background layer to
				the top edge of input 0.
	5	Input 0	enable	Input 0 is displayed if you set this control register to 1.
6		Reserved		Reserved for future use.
	7	Reserved		Reserved for future use.
8		Input 1	X	X offset in pixels from the left edge of the background layer to
				the left edge of input 1.
	9	Input 1	Y	Y offset in pixels from the top edge of the background layer to
				the top edge of input 1.
	10	Input 1	enable	Input 1 is displayed if you set this control register to 1.
	11	Reserved		Reserved for future use.
12		Reserved		Reserved for future use.
	13	Input 2	X	X offset in pixels from the left edge of the background layer to
				the left edge of input 2.
	14	Input 2	Y	Y offset in pixels from the top edge of the background layer to
				the top edge of input 2.
	15	Input 2	enable	Input 2 is displayed if you set this control register to 1.
16		Reserved		Reserved for future use.
	17	Reserved		Reserved for future use.
18		Input 3	X	X offset in pixels from the left edge of the background layer to
				the left edge of input 3.
	19	Input 3	Y	Y offset in pixels from the top edge of the background layer to
				the top edge of input 3.
	20	Input 3	enable	Input 3 is displayed if you set this control register to 1.
	21	Reserved		Reserved for future use.
22		Reserved		Reserved for future use.
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