UG-VIPSUITE				In-System Performance and Resource Guidance			1-7
2015.01.23
	IP Core			Mode		Latency
			•	Method: Motion-adaptive		1 field + 2 lines
			•	Frame buffering: None
			• Output frame rate: As input
				field rate
			•	Method: Motion-adaptive,		1 field + 2 lines, or 2 lines
				video-over-film mode
	Broadcast Deinterlacer		• Frame buffering: 3 input
				fields are buffered
			• Output frame rate: As input
				field rate
			40% to 60% (depending on
			phasing) of the time, the core
			performs a weave forward so
			there is no initial field of latency.
	Frame Buffer/ Frame Buffer II		All modes			1 frame + O (lines)
	Frame Reader		No latency issues.
	Gamma Corrector		All modes			O (cycles)
	Interlacer		All modes			O (cycles)
	Scaler II		•	Scaling algorithm: Polyphase		(N–1) lines + O (cycles)
			• Number of vertical taps: N
	Switch/ Switch II		All modes			2 cycles
	Test Pattern Generator/		No latency issues.
	Test Pattern Generator II

In-System Performance and Resource Guidance

The performance and resource data provided for your guidance.

Note: Run your own synthesis and fMAX trials to confirm the listed IP cores meet your system require ments.

Video and Image Processing Suite Overview	Altera Corporation

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	1-8	In-System Performance and Resource Guidance	UG-VIPSUITE
			2015.01.23

Table 1-5: Performance and Resource Data Using Arria V Devices

The following data are obtained through a 4K test design example using an Arria V device (5AGXFB3H4F35C4). The general settings for the design is 8 bits per color plane; 2 pixels in parallel. The target fMAX is 148.5 MHz.

IP Core			Configuration		ALM		RAM		DSP
Mixer II		•	Number of color planes in parallel = 3		1,591		0		0
		•	Inputs = 4
		•	Output = 1
		• Internal Test Pattern Generator
Clocked Video		•	Number of color planes in parallel = 3		540		26		0
Input II		• Sync signals = On separate wires
		• Pixel FIFO size = 4096 pixels
		• Use control port = On
Clocked Video		•	Number of color planes in parallel = 3		2,504		49		0
Output II		• Sync signals = On separate wires
		• Pixel FIFO size = 4096 pixels
		• Use control port = On
		• Run-time configurable video modes = 4
Color Space		•	Run-time control = On		1,515		0		18
Converter II		• Color model conversion = RGb to YCbCr
Broadcast Deinter		•	Number of color planes in parallel = 2		11,516		145		34
lacer		• Avalon-MM master local ports width =
			256
		• FIFO depths = 512
		• Run-time control = Off
Frame Buffer II		•	Number of color planes in parallel = 2		1,472		19		0
		• Avalon-MM master ports width = 256
		• Read/write FIFO depth = 128
		• Frame dropping = On
		• Frame repeating = On
Test Pattern		•	Color space = RGB		135		0		0
Generator II		• Run-time control of image size = On

Altera Corporation	Video and Image Processing Suite Overview

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	UG-VIPSUITE	In-System Performance and Resource Guidance	1-9
	2015.01.23

Table 1-6: Performance and Resource Data Using Cyclone V Devices

The following data are obtained through a video design example using a Cyclone V device (5CGTFD9E5F35C7). The general setting for the design is 8 bits per color plane. The target fMAX is 100 MHz.

	IP Core		Configuration		ALM		RAM		DSP
	2D FIR Filter		• Number of color planes in sequence = 3		581		10		3
			• Filter size = 3×3
			• Runtime control = On
			• Integer bits = 4
			• Fractional bits = 3
	Avalon-ST Video		• Number of color planes in parallel = 3		1,035		10		0
	Monitor		• Capture video pixel data = On
	Avalon-ST Video		• Number of color planes in parallel = 3		479		9		0
	Monitor		• Capture video pixel data = Off
	Alpha Blending		• Number of color planes in parallel = 3		1,324		1		24
	Mixer		• Number of layers being mixed = 5
			• Alpha blending = On
	Chroma		• 4:2:2, number of color planes in parallel		591		0		0
	Resampler		(din) = 2
			• 4:4:4, number of color planes in parallel
			(dout) = 3
			• Horizontal filtering algorithm = Filtered
			• Luma adaptive = On
	Clipper II		• Number of pixels (color planes) in parallel		402		0		0
			= 3
			• Clipping method = Rectangle
			• Enable runtime control of clipping
			parameters = On
	Clocked Video		• Number of color planes in parallel = 3		257		13		0
	Input		• Sync signals = On separate wires
			• Pixel FIFO size = 2048 pixels
			• Use control port = On
	Clocked Video		• Number of color planes in sequence = 2		317		9		0
	Input		• Sync signals = Embedded
			• Pixel FIFO size = 2048 pixels
			• Use control port = On
Video and Image Processing Suite Overview									Altera Corporation
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1-10		In-System Performance and Resource Guidance								UG-VIPSUITE
									2015.01.23
		IP Core		Configuration		ALM		RAM		DSP
		Clocked Video		• Number of color planes in parallel = 3		512		5		0
		Output		• Sync signals = On separate wires
				• Pixel FIFO size = 1024 pixels
				• Use control port = On
				• Run-time configurable video modes = 1
		Color Plane		• din0: Color planes in parallel = 4		104		0		0
		Sequencer		• dout0: Color planes in parallel = 3
				• dout1: Color planes in parallel = 1
		Color Space		• Color plane configuration = Three color		284		0		9
		Converter		planes in parallel
				• Run-time control = Off
				• Color model conversion = CbCrY': SDTV
				to Computer B'G'R'
				• Coefficients integer bits = 2
				• Summands integer bits = 9
				• Coefficient and summand fractional bits =
				8
		Deinterlacer II		• Number of color planes in parallel = 3		3,655		67		3
				• Deinterlace algorithm = Motion adaptive
				• Cadence detection algorithm = 3:2 detector
				• Avalon-MM master local ports width =
				128
				• FIFO depths = 64
		Frame Buffer		• Number of color planes in parallel = 3		1,084		19		0
				• Avalon-MM master ports width = 128
				• Read/write FIFO depth = 64
				• Frame dropping = On
				• Frame repetition = On
		Frame Reader		• Number of color planes in parallel = 4		756		6		0
				• Avalon-MM master port width = 128
				• Read master FIFO depth = 64
				• Use separate clocks for the Avalon-MM
				master interfaces = On
		Gamma Corrector		Number of color planes in parallel = 3		142		3		0

Altera Corporation	Video and Image Processing Suite Overview

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