17-12		Scaler II Signals					UG-VIPSUITE
						2015.01.23
		Parameter			Value		Description
		Horizontal coefficient banks		1–32, Default = 1			Select the number of banks of horizontal filter
							coefficients for polyphase algorithms.
		Horizontal coefficient function		•	Lanczos_2		Select the function used to generate the
				•	Lanczos_3		horizontal scaling coefficients. Select either
							one for the pre-defined Lanczos functions or
				•	Custom
							choose Custom to use the coefficients saved
							in a custom coefficients file.
		Horizontal coefficients file		User-specified			When a custom function is selected, you can
							browse for a comma-separated value file
							containing custom coefficients. Key in the
							path for the file that contains these custom
							coefficients.
		Add extra pipelining registers		On or Off			Turn on to add extra pipeline stage registers
							to the data path.
							You must to turn on this option to achieve:
							• frequency of 150 MHz for Cyclone III or
							Cyclone IV devices
							• frequencies above 250 MHz for Arria II,
							Stratix IV, or Stratix V devices

Scaler II Signals

Table 17-3: Common Signals

		Signal		Directio		Description
				n
	main_clock			Input		The main system clock. The IP core operates on the
						rising edge of this signal.
	main_reset			Input		The IP core asynchronously resets when you assert this
						signal. You must deassert this signal synchronously to
						the rising edge of the main_clock signal.
	din_data			Input		din port Avalon-ST data bus. This bus enables the
						transfer of pixel data into the IP core.
	din_endofpacket			Input		din port Avalon-ST endofpacket signal. This signal
						marks the end of an Avalon-ST packet.
	din_ready			Output		din port Avalon-ST ready signal. This signal indicates
						when the IP core is ready to receive data.
	din_startofpacket			Input		din port Avalon-ST startofpacket signal. This signal
						marks the start of an Avalon-ST packet.
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UG-VIPSUITE					Scaler II Signals	17-13
2015.01.23
	Signal		Directio		Description
			n
	din_valid		Input		din port Avalon-ST valid signal. This signal identifies
					the cycles when the port must enter data.
	dout_data		Output		dout port Avalon-ST data bus. This bus enables the
					transfer of pixel data out of the IP core.
	dout_endofpacket		Output		dout port Avalon-ST endofpacket signal. This signal
					marks the end of an Avalon-ST packet.
	dout_ready		Input		dout port Avalon-ST ready signal. The downstream
					device asserts this signal when it is able to receive data.
	dout_startofpacket		Output		dout port Avalon-ST startofpacket signal. This signal
					marks the start of an Avalon-ST packet.
	dout_valid		Output		dout port Avalon-ST valid signal. The IP core asserts
					this signal when it produces data.

Table 17-4: Control Signals

Note: These signals are present only if you turn on Enable run-time control of input/output frame size and turn off Bilinear for Scaling algorithm in the Scaler II parameter editor.

Signal		Directio		Description
		n

	control_address	Input	control slave port Avalon-MM address bus. This bus
			specifies a word offset in the Avalon-MM address space.
	control_byteenable	Input	control slave port Avalon-MM byteenable bus. This
			bus enables specific byte lane or lanes during transfers.
			Each bit in byteenable corresponds to a byte in
			writedata and readdata.
			• During writes, this bus specifies which bytes are being
			written to; other bytes are ignored by the slave.
			• During reads, this bus indicates which bytes the
			master is reading. Slaves that simply return readdata
			with no side effects are free to ignore this bus during
			reads.
	control_read	Output	control slave port Avalon-MM read signal. When you
			assert this signal, the control port sends new data at
			readdata.
	control_readdata	Output	control slave port Avalon-MM control_data bus. The
			IP core uses these output lines for read transfers.
	control_readdatavalid	Output	control slave port Avalon-MM readdata bus. When
			you assert this signal, the control port sends new data at
			control_readdata.
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	17-14	Scaler II Control Registers	UG-VIPSUITE
			2015.01.23

Signal		Directio		Description
		n
control_waitrequest		Output		control slave port Avalon-MM waitrequest signal.
control_write		Input		control slave port Avalon-MM write signal. When you
				assert this signal, the control port accepts new data from
				the writedata bus.
control_writedata		Input		control slave port Avalon-MM writedata bus. The IP
				core uses these input lines for write transfers.

Scaler II Control Registers

The control data is read once at the start of each frame and is buffered inside the IP core, so the registers can be safely updated during the processing of a frame.

Table 17-5: Scaler II Control Register Map

The coefficient bank that is being read by the IP core must not be written to unless the core is in a stopped state. To change the contents of the coefficient bank while the IP core is in a running state, you must use multiple coefficient banks to allow an inactive bank to be changed without affecting the frame currently being processed. The Scaler II IP core allows for dynamic bus sizing on the slave interface. The slave interface includes a 4-bit byte enable signal, and the width of the data on the slave interface is 32 bits.

Note: The Ntaps is the number of horizontal or vertical filter taps, whichever is larger.

Address		Register		Description
0		Control		• Bit 0 of this register is the Go bit, all other bits are unused.
				Setting this bit to 0 causes the IP core to stop the next time
				control information is read.
				• Bit 1 enables the edge adaptive coefficient selection—set to
				1 to enable this feature.
				• Bit 2 enables edge adaptive sharpening—set to 1 to enable
				this feature.
1		Status		Bit 0 of this register is the Status bit, all other bits are unused.
				• It is set to 0 if the IP core has not been started.
				• It is set to 1 while the IP core is processing data and cannot
				be stopped.
2		Interrupt		This bit is not used because the IP core does not generate any
				interrupts.
3		Output Width		The width of the output frames in pixels.
4		Output Height		The height of the output frames in pixels.

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UG-VIPSUITE					Scaler II Control Registers	17-15
2015.01.23
	Address		Register		Description
	5		Edge Threshold		Specifies the minimum difference between neighboring pixels
					beyond which the edge-adaptive algorithm switches to using
					the edge coefficient set. To get the threshold used internally,
					this value is multiplied by the number of color planes per
					pixel.
	6		Lower Blur Threshold		Specifies the minimum difference between two pixels for a
					blurred edge to be detected between the pixels during post
					scaling edge-adaptive sharpening. To get the threshold used
					internally, this value is multiplied by the number of color
					planes per pixel.
	7		Upper Blur Threshold		Specifies the maximum difference between two pixels for a
					blurred edge to be detected between the pixels during post
					scaling edge-adaptive sharpening. To get the threshold used
					internally, this value is multiplied by the number of color
					planes per pixel.
	8		Horizontal		Specifies which memory bank horizontal coefficient writes
			Coefficient Write		from the Avalon-MM interface are made into.
			Bank
	9		Horizontal		Specifies which memory bank is used for horizontal
			Coefficient Read		coefficient reads during data processing.
			Bank
10			Vertical Coefficient		Specifies which memory bank vertical coefficient writes from
			Write Bank		the Avalon-MM interface are made into.
	11		Vertical Coefficient		Specifies which memory bank is used for vertical coefficient
			Read Bank		reads during data processing.
	12		Horizontal Phase		Specifies which horizontal phase the coefficient tap data in the
					Coefficient Data register applies to. Writing to this
					location, commits the writing of coefficient tap data. This
					write must be made even if the phase value does not change
					between successive sets of coefficient tap data.
					To commit to an edge phase, write the horizontal phase
					number +32768. For example, set bit 15 of the register to 1.
	13		Vertical Phase		Specifies which vertical phase the coefficient tap data in the
					Coefficient Data register applies to. Writing to this
					location, commits the writing of coefficient tap data. This
					write must be made even if the phase value does not change
					between successive sets of coefficient tap data.
					To commit to an edge phase, write the vertical phase number
					+32768. For example, set bit 15 of the register to 1.

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	17-16	Scaler II Control Registers	UG-VIPSUITE
			2015.01.23

Address		Register		Description

14 to 14+Ntaps	Coefficient Data	Specifies values for the coefficients at each tap of a particular
		horizontal or vertical phase. Write these values first, then the
		Horizontal Phase or Vertical Phase, to commit the write.

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