14-14	Frame Buffer Control Registers	UG-VIPSUITE
			2015.01.23

Frame Buffer Control Registers

A run-time control can be attached to either the writer component or the reader component of the Frame Buffer IP cores but not to both. The width of each register is 16 bits.

Table 14-8: Frame Buffer Control Register Map for the Writer

The table below describes the control register map for the writer component.

Note: Addresses 4, 5, and 6 are optional and only visible on the control interface when you turn on Support lock frame rate conversion in the parameter editor.

Address		Register		Description
0		Control		Bit 0 of this register is the Go bit, all other bits are unused.
				Setting this bit to 0 causes the IP core to stop the next time
				control information is read.
1		Status		Bit 0 of this register is the Status bit, all other bits are unused.
2		Frame Counter		Read-only register updated at the end of each frame processed
				by the writer. The counter is incremented if the frame is not
				dropped and passed to the reader.
3		Drop Counter		Read-only register updated at the end of each frame processed
				by the writer. The counter is incremented if the frame is
				dropped.
4		Controlled Rate		Bit 0 of this register determines whether dropping and
		Conversion		repeating of frames or fields is tightly controlled by the
				specified input and output frame rates. Setting this bit to 0
				switches off the controlled rate conversion, and returns the
				triple-buffering algorithm to a free regime where dropping
				and repeating is only determined by the status of the spare
				buffer.
5		Input Frame Rate		Write-only register. A 16-bit integer value for the input frame
				rate. This register cannot be read.
6		Output Frame Rate		Write-only register. A 16-bit integer value for the output
				frame rate. This register cannot be read.

Table 14-9: Frame Buffer Control Register Map for the Reader

The table below describes the control register map for the reader component.

Address		Register		Description
0		Control		Bit 0 of this register is the Go bit, all other bits are unused.
				Setting this bit to 0 causes the IP core to stop the next time
				control information is updated. While stopped, the IP core
				may continue to receive and drop frame at its input if you
				enable frame dropping.

Altera Corporation	Frame Buffer IP Cores

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UG-VIPSUITE					Frame Buffer Control Registers	14-15
2015.01.23
	Address		Register		Description
	1		Status		Bit 0 of this register is the Status bit, all other bits are unused.
2			Frame Counter		Read-only register updated at the end of each frame processed
					by the reader. The counter is incremented if the frame is not
					repeated.
	3		Repeat Counter		Read-only register updated at the end of each frame processed
					by the reader. The counter is incremented if the frame is
					about to be repeated.

Table 14-10: Frame Buffer II Control Register Map for the Writer

The table below describes the control register map for the writer component.

Note: Addresses 4, 5, and 6 are optional and only visible on the control interface when you turn on Locked rate support in the parameter editor.

	Address		Register		Description
0			Control		Bit 0 of this register is the Go bit, all other bits are unused.
					Setting this bit to 0 causes the IP core to stop the next time
					control information is read.
	1		Status		Bit 0 of this register is the Status bit, all other bits are unused.
2			Interrupt		Bits 2 and 1 are the interrupt status bits:
					• When bit 1 is asserted, the status update interrupt has
					triggered.
					• When bit 2 is asserted, the stable video interrupt has
					triggered.
					• The interrupts stay asserted until a 1 is written to these
					bits.
	3		Frame Counter		Read-only register updated at the end of each frame processed
					by the writer. The counter is incremented if the frame is not
					dropped and passed to the reader.
	4		Drop Counter		Read-only register updated at the end of each frame processed
					by the writer. The counter is incremented if the frame is
					dropped.
	5		Controlled Rate		Bit 0 of this register determines whether dropping and
			Conversion		repeating of frames or fields is tightly controlled by the
					specified input and output frame rates. Setting this bit to 0
					switches off the controlled rate conversion, and returns the
					triple-buffering algorithm to a free regime where dropping
					and repeating is only determined by the status of the spare
					buffer.
	6		Input Frame Rate		Write-only register. A 16-bit integer value for the input frame
					rate. This register cannot be read.
Frame Buffer IP Cores						Altera Corporation
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	14-16		Frame Buffer Control Registers				UG-VIPSUITE
						2015.01.23
			Address		Register		Description
		7			Output Frame Rate		Write-only register. A 16-bit integer value for the output
							frame rate. This register cannot be read.

Table 14-11: Frame Buffer II Control Register Map for the Reader

The table below describes the control register map for the reader component.

Address		Register		Description
0		Control		Bit 0 of this register is the Go bit, all other bits are unused.
				Setting this bit to 0 causes the IP core to stop the next time
				control information is updated. While stopped, the IP core
				may continue to receive and drop frame at its input if you
				enable frame dropping.
1		Status		Bit 0 of this register is the Status bit, all other bits are unused.
2		Interrupt		Bits 2 and 1 are the interrupt status bits:
				• When bit 1 is asserted, the status update interrupt has
				triggered.
				• When bit 2 is asserted, the stable video interrupt has
				triggered.
				• The interrupts stay asserted until a 1 is written to these
				bits.
3		Frame Counter		Read-only register updated at the end of each frame processed
				by the reader. The counter is incremented if the frame is not
				repeated.
4		Repeat Counter		Read-only register updated at the end of each frame processed
				by the reader. The counter is incremented if the frame is
				about to be repeated.

Altera Corporation	Frame Buffer IP Cores

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