- •Contents
- •1. Video and Image Processing Suite Overview
- •Release Information
- •Device Family Support
- •Latency
- •In-System Performance and Resource Guidance
- •Stall Behavior and Error Recovery
- •2. Interfaces
- •Video Formats
- •Avalon-ST Video Protocol
- •Video Data Packets
- •Static Parameters of Video Data Packets
- •Control Data Packets
- •Ancillary Data Packets
- •User-Defined and Altera-Reserved Packets
- •Packet Propagation
- •Transmission of Avalon-ST Video Over Avalon-ST Interfaces
- •Packet Transfer Examples
- •Avalon-MM Slave Interfaces
- •Specification of the Type of Avalon-MM Slave Interfaces
- •Avalon-MM Master Interfaces
- •Specification of the Type of Avalon-MM Master Interfaces
- •Buffering of Non-Image Data Packets in Memory
- •3. Getting Started
- •IP Catalog and Parameter Editor
- •Specifying IP Core Parameters and Options
- •Installing and Licensing IP Cores
- •OpenCore Plus IP Evaluation
- •4. Clocked Video Interface IP Cores
- •Control Port
- •Clocked Video Input Format Detection
- •Interrupts
- •Clocked Video Output Video Modes
- •Interrupts
- •Generator Lock
- •Underflow and Overflow
- •Timing Constraints
- •Handling Ancillary Packets
- •Modules for Clocked Video Input II IP Core
- •Clocked Video Interface Parameter Settings
- •Clocked Video Interface Signals
- •Clocked Video Interface Control Registers
- •5. 2D FIR Filter IP Core
- •Calculation Precision
- •Coefficient Precision
- •Result to Output Data Type Conversion
- •2D FIR IP Core Parameter Settings
- •2D FIR Filter Signals
- •2D FIR Filter Control Registers
- •6. Video Mixing IP Cores
- •Alpha Blending
- •Video Mixing Parameter Settings
- •Video Mixing Signals
- •Video Mixing Control Registers
- •7. Chroma Resampler IP Core
- •Horizontal Resampling (4:2:2)
- •Vertical Resampling (4:2:0)
- •Chroma Resampler Parameter Settings
- •Chroma Resampler Signals
- •8. Video Clipping IP Cores
- •Video Clipping Parameter Settings
- •Video Clipping Signals
- •Video Clipping Control Registers
- •9. Color Plane Sequencer IP Core
- •Combining Color Patterns
- •Rearranging Color Patterns
- •Splitting and Duplicating
- •Subsampled Data
- •Color Plane Sequencer Parameter Settings
- •Color Plane Sequencer Signals
- •10. Color Space Conversion IP Cores
- •Input and Output Data Types
- •Color Space Conversion
- •Result of Output Data Type Conversion
- •Color Space Conversion Parameter Settings
- •Color Space Conversion Signals
- •Color Space Conversion Control Registers
- •11. Control Synchronizer IP Core
- •Using the Control Synchronizer IP Core
- •Control Synchronizer Parameter Settings
- •Control Synchronizer Signals
- •Control Synchronizer Control Registers
- •12. Deinterlacing IP Cores
- •Deinterlacing Methods
- •Bob with Scanline Duplication
- •Bob with Scanline Interpolation
- •Weave
- •Motion-Adaptive
- •Sobel-Based HQ Mode
- •Pass-Through Mode for Progressive Frames
- •Frame Buffering
- •Frame Rate Conversion
- •Bandwidth Requirement Calculations for 10-bit YCbCr Video
- •Behavior When Unexpected Fields are Received
- •Handling of Avalon-ST Video Control Packets
- •Deinterlacing Parameter Settings
- •Deinterlacing Signals
- •Deinterlacing Control Registers
- •Design Guidelines for Broadcast Deinterlacer IP Core
- •13. Frame Reader IP Core
- •Single-Cycle Color Patterns
- •Frame Reader Output Pattern and Memory Organization
- •Frame Reader Parameter Settings
- •Frame Reader Signals
- •Frame Reader Control Registers
- •14. Frame Buffer IP Cores
- •Double Buffering
- •Triple Buffering
- •Locked Frame Rate Conversion
- •Handling of Avalon-ST Video Control Packets
- •Color Format
- •Frame Buffer Parameter Settings
- •Frame Buffer Signals
- •Frame Buffer Control Registers
- •15. Gamma Corrector IP Core
- •Gamma Corrector Parameter Settings
- •Gamma Corrector Signals
- •Gamma Corrector Control Registers
- •16. Interlacer IP Core
- •Interlacer Parameter Settings
- •Interlacer Signals
- •Interlacer Control Registers
- •17. Scaler II IP Core
- •Nearest Neighbor Algorithm
- •Bilinear Algorithm
- •Bilinear Algorithmic Description
- •Polyphase and Bicubic Algorithm
- •Double-Buffering
- •Polyphase Algorithmic Description
- •Choosing and Loading Coefficients
- •Edge-Adaptive Scaling Algorithm
- •Scaler II Parameter Settings
- •Scaler II Signals
- •Scaler II Control Registers
- •18. Video Switching IP Cores
- •Mixer Layer Switching
- •Video Switching Parameter Settings
- •Video Switching Signals
- •Video Switching Control Registers
- •19. Test Pattern Generator IP Cores
- •Test Pattern
- •Generation of Avalon-ST Video Control Packets and Run-Time Control
- •Test Pattern Generator Parameter Settings
- •Test Pattern Generator Signals
- •Test Pattern Generator Control Registers
- •20. Trace System IP Core
- •Trace System Parameter Settings
- •Trace System Signals
- •Operating the Trace System from System Console
- •Loading the Project and Connecting to the Hardware
- •Trace Within System Console
- •TCL Shell Commands
- •21. Avalon-ST Video Monitor IP Core
- •Packet Visualization
- •Monitor Settings
- •Avalon-ST Video Monitor Parameter Settings
- •Avalon-ST Video Monitor Signals
- •Avalon-ST Video Monitor Control Registers
- •Avalon-ST Video Class Library
- •Running the Tests
- •Video File Reader Test
- •Example Test Environment
- •Video Field Life Cycle
- •Constrained Random Test
- •Complete Class Reference
- •c_av_st_video_control
- •c_av_st_video_data
- •c_av_st_video_file_io
- •c_av_st_video_item
- •c_av_st_video_source_sink_base
- •c_av_st_video_sink_bfm_’SINK
- •c_av_st_video_source_bfm_’SOURCE
- •c_av_st_video_user_packet
- •c_pixel
- •Raw Video Data Format
- •Cadence Detection and Reverse Pulldown in the Deinterlacer II IP Core
- •Document Revision History
- •How to Contact Altera
UG-VIPSUITE |
Constrained Random Test |
A-13 |
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2015.01.23 |
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Stage |
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Description |
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Stage 2 |
• After the reader assembles a complete video object, the reader casts the |
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video object into the base class (c_av_st_video_item). This code is for this |
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base class: |
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typedef c_av_st_video_data #(BITS_PER_CHANNEL, CHANNELS_ |
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PER_PIXEL) video_t; |
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item_data = video_t'(video_data); |
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• After the reader casts the video object into the base class, it sends the video |
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object to the mailbox. |
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Stage 3 |
• The video source BFM retrieves the data from its mailbox, recasts the data |
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back into a c_av_st_video_data video object, and begins translating it into |
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transactions for the Avalon-ST source BFM. |
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• To indicate that a video packet is being sent, there is one transaction per |
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pixel and an initial transaction with LSBs of 0×0 when using RGB24 data, |
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24-bit data buses, and parallel transmission. |
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Stage 4 |
The Avalon-ST source BFM turns each transaction into beats of data on the |
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Avalon-ST bus, which are received by the DUT. |
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Stage 5 |
• The DUT processes the data and presents the output data on the Avalon-ST |
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bus. |
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• The Avalon-ST Sink BFM receives these and triggers a signal_transaction_ |
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received event for each beat. |
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Stage 6 |
• After the video sink BFM detects the signal_transaction_received |
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event, the video sink BFM starts collecting transaction data from the BFM. |
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• When a start of packet (SOP) beat is detected, the type of the packet is |
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verified, and transaction data is pushed into a pixel object, which is in turn |
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pushed into a video_data object. |
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Stage 7 |
• An end of packet (EOP) is seen in the incoming transactions, the video sink |
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BFM casts the video data into a c_av_st_video_item object, and transfers the |
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data into its mailbox. |
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• The file writer then receives the video item. |
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Stage 8 |
The file writer recasts the video item to a video data packet, pops off the pixel, |
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and writes the data to the output file as binary data. |
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Constrained Random Test
The constrained random test is easily assembled using the class library.
Avalon-ST Video Verification IP Suite |
Altera Corporation |
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Send Feedback
A-14 |
Constrained Random Test |
UG-VIPSUITE |
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2015.01.23 |
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Figure A-6: Example of a Constrained Random Test Environment
The figure below shows the constrained random test environment structure.
tb_test.v (test environment)
tb.v (netlist) |
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Avalon-ST |
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AV-ST |
Avalon-ST |
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bus |
DUT |
bus |
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Source BFM |
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module |
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module |
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function call |
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function call |
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interface |
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interface |
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Avalon-ST |
Avalon-ST |
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Video Source |
Video Sink BFM |
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mailbox |
BFM |
object |
mailbox |
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object |
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Random |
m_video_items_for_src_bfm |
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m_video_items_ |
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video item |
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for_sink_bfm |
Scoreboard |
generation |
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mailbox |
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m_video_items_for_scoreboard |
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The randomized video and control and user packets are generated using the SystemVerilog’s built-in constrained random features. The DUT processes the video packets and the scoreboard determines a test pass or fail result..
Altera Corporation |
Avalon-ST Video Verification IP Suite |
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Send Feedback
UG-VIPSUITE 2015.01.23
Constrained Random Test |
A-15 |
• Code for constrained random generation
fork
`SOURCE.start();
`SINK.start();
forever begin
// Randomly determine which packet type to send : r = $urandom_range(100, 0);
if (r>67) begin
video_data_pkt1.set_max_length(100); video_data_pkt1.randomize(); video_data_pkt1.populate();
// Send it to the source BFM : m_video_items_for_src_bfm.put(video_data_pkt1);
// Copy and send to scoreboard : video_data_pkt2 = new(); video_data_pkt2.copy(video_data_pkt1);
m_video_items_for_scoreboard.put(video_data_pkt2);
end
else if (r>34) begin
video_control_pkt1.randomize(); m_video_items_for_src_bfm.put(video_control_pkt1);
// Copy and send to scoreboard : video_control_pkt2 = new(); video_control_pkt2.copy(video_control_pkt1);
m_video_items_for_scoreboard.put(video_control_pkt2);
end
else begin
user_pkt1.set_max_length(33); user_pkt1.randomize() ; m_video_items_for_src_bfm.put(user_pkt1);
// Copy and send to scoreboard : user_pkt2 = new(); user_pkt2.copy(user_pkt1);
m_video_items_for_scoreboard.put(user_pkt2);
end
// Video items have been sent to the DUT and the scoreboard, //wait for the analysis :
-> event_constrained_random_generation; wait(event_dut_output_analyzed);
end
join
This code starts the source and sink, then randomly generates either a video data, control or user packet. Generation is achieved by simply calling randomize() on the objects previously created at the end of this code, putting the objects in the source BFM’s mailbox (m_video_items_for_src_bfm), making a copy of the objects, and putting that in a reference mailbox used by the scoreboard
(m_video_items_for_scoreboard).
Finally, the code signals to the scoreboard that a video item has been sent and waits for the output of
Avalon-ST Video Verification IP Suite Altera Corporation the DUT to be analyzed, also signalled by an event from the scoreboard.
Send FeedbackAll that remains now is to create the scoreboard, which retrieves the video item objects from the two scoreboard mailboxes and compares the ones from the DUT with the reference objects.
Note: The scoreboard expects to see the DUT returning greyscale video data. You must customize the data to mirror the behavior of individual DUTs exactly..