Trace System IP Core 20

2015.01.23

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The Trace System IP core is a debugging and monitoring component.

The trace system collects data from various monitors, such as the Avalon-ST monitor, and passes it to System Console software on the attached debugging host. System Console software captures and visualizes the behavior of the attached system. You can transfer data to the host over one of the following connections:

•Direct USB connection with a higher bandwidth; for example On-Board USB-Blaster™ II

•If you select the USB connection to the host, the trace system exposes the usb_if interface.

•Export this interface from the Qsys system and connect to the pins on the device that connects to the On-Board USB-Blaster II.

Note: To manually connect the usb_if conduit, use the USB Debug Link component, located in

Verification > Debug & Performance.

•JTAG connection

•If you select the JTAG connection to the host, then the Quartus II software automatically makes the pin connection during synthesis.

The Trace System IP core transports messages describing the captured events from the trace monitor components, such as the Frame Reader, to a host computer running the System Console software.

Figure 20-1: Trace System Functional Block Diagram

Conduit for connection to pins (USB only)

	Altera Trace System	Avalon-ST Source
		(capture)
		Monitor #1
Link to Host	Buffering	Avalon-MM Slave
		(control)
		Monitor #2

When you instantiate the Trace System IP core, turn on the option to select the number of monitors required. The trace system exposes a set of interfaces: capturen and controln. You must connect each pair of the interfaces to the appropriate trace monitor component.

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	20-2	Trace System Parameter Settings	UG-VIPSUITE
			2015.01.23

The IP core provides access to the control interfaces on the monitors. You can use these control ports to change the capture settings on the monitors; for example, to control the type of information captured by the monitors or to control the maximum data rate sent by the monitor.

Note: Each type of monitor is different. Refer to the relevant documentation of the monitors for more information.

Each trace monitor sends information about interesting events through its capture interface. The trace system multiplexes these data streams together and, if the trace system is running, stores them into a FIFO buffer. The contents of this buffer are streamed to the host using as much as the available trace bandwidth.

The amount of buffering required depends on the amount of jitter inserted by the link, in most cases, the default value of 32Kbytes is sufficient.

Note: The System Console uses the sopcinfo file written by Qsys to discover the connections between the Trace System IP core and the monitors. If you instantiate and manually connect the Trace System IP core and the monitors using HDL, the System Console will not detect them.

Trace System Parameter Settings

Table 20-1: Trace System Parameter Settings

Parameter			Value		Description
Export interfaces for connection		Yes or No			If you select USB as the connection to host,
to manual debug fabric					selecting Yes shows the usb_if conduit—
					enables you to manually connect this
					interface.
Connection to host		•	JTAG		Select the type of connection to the host
		•	USB		running the System Console.
Bit width of capture interface(s)		8–128, Default = 32			Select the data bus width of the Avalon-ST
					interface sending the captured information.
Number of inputs		2–16, Default = 2			Select the number of trace monitors which
					will be connected to this trace system.
Buffer size		8192–65536, Default =			Select the size of the jitter buffer in bytes.
		32768
Insert pipeline stages		On or Off			Turn on to insert the pipeline stages within
					the trace system. Turning on this parameter
					gives a higher fmax but uses more logic.

Altera Corporation	Trace System IP Core

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	UG-VIPSUITE	Trace System Signals	20-3
	2015.01.23

Trace System Signals

Table 20-2: Trace System Signals

	Signal		Direction		Description
	clk_clk		Input		All signals on the trace system are synchronous to this
					clock.
					Do not insert clock crossing between the monitor and
					the trace system components. You must drive the
					trace monitors’ clocks from the same source which
					drives this signal.
	reset_reset		Output		This signal is asserted when the IP core is being reset
					by the debugging host. Connect this signal to the reset
					inputs on the trace monitors.
					Do not reset parts of the system being monitored with
					this signal because this will interfere with function
					ality of the system.
	usb_if_clk		Input		Clock provided by On-Board USB-Blaster II.
					All usb_if signals are synchronous to this clock; the
					trace system provides clock crossing internally.
	usb_if_reset_n		Input		Reset driven by On-Board USB-Blaster II.
	usb_if_full		Output		Host to the target full signal.
	usb_if_empty		Output		Target to the host empty signal.
	usb_if_wr_n		Input		Write enable to the host to target FIFO.
	usb_if_rd_n		Input		Read enable to the target to host FIFO.
	usb_if_oe_n		Input		Output enable for data signals.
	usb_if_data		Bidirectional		Shared data bus.
	usb_if_scl		Input		Management interface clock.
	usb_if_sda		Input		Management interface data.
	capturen_data		Input		capturen port Avalon-ST data bus. This bus enables
					the transfer of data out of the IP core.
	capturen_endofpacket		Input		capturen port Avalon-ST endofpacket signal. This
					signal marks the end of an Avalon-ST packet.
	capturen_empty		Input		capturen port Avalon-ST empty signal.
	capturen_ready		Output		capturen port Avalon-ST ready signal. The
					downstream device asserts this signal when it is able
					to receive data.
Trace System IP Core						Altera Corporation
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