Interlacer IP Core 16

2015.01.23

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The Interlacer IP core converts progressive video to interlaced video by dropping half the lines of incoming progressive frames.

The Interlacer IP core generates an interlaced stream by dropping half the lines of each progressive input frame. The IP core drops odd and even lines in successive order to produce an alternating sequence of F0 and F1 fields. The output field rate is consequently equal to the input frame rate.

The Interlacer IP core handles changing input resolutions by reading the content of Avalon-ST Video control packets. The IP core supports incoming streams where the height of the progressive input frames is an odd value. In such a case, the height of the output F0 fields are one line higher than the height of the output F1 fields.

When the input stream is already interlaced, the IP core either discards the incoming interlaced fields or propagates the fields without modification, based on the compile time parameters you specify. When you turn on Run-time control in the parameter editor, you can also deactivate the Interlacer IP core at run time to prevent the interlacing and propagate a progressive video stream without modification.

At start up or after a change of input resolution, the Interlacer IP core begins the interlaced output stream by dropping odd lines to construct a F0 field or by dropping even lines to construct a F1 field, based on the compile time parameters you specify.

Alternatively, when you turn on Control packets override field selection parameter and the interlace nibble indicates that the progressive input previously went through a deinterlacer (0000 or 0001), the Interlacer IP core produces:

•a F0 field if the interlace nibble is 0000

•a F1 field if the interlace nibble is 0001

Note: For most systems, turn off Control packets override field selection parameter to guarantee the Interlacer IP core produces a valid interlaced video output stream where F0 and F1 fields alternate in regular succession.

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	16-2	Interlacer Parameter Settings	UG-VIPSUITE
			2015.01.23

Interlacer Parameter Settings

Table 16-1: Interlacer Parameter Settings

Parameter			Value		Description
Maximum image width		32–2600, Default = 640			Specify the maximum frame width in pixels.
					The maximum frame width is the default
					width at start-up.
Maximum image height		32–2600, Default = 480			Specify the maximum progressive frame
					height in pixels. The maximum frame height
					is the default progressive height at start-up.
Bits per pixel per color plane		4–20, Default = 8			Select the number of bits per pixel (per color
					plane).
Number of color planes in		1–3, Default = 3			Select the number of color planes that are
sequence					sent in sequence over one data connection.
					For example, a value of 3 for R'G'B' R'G'B'
					R'G'B'.
Number of color planes in		1–3, Default = 1			Select the number of color planes sent in
parallel					parallel.
Initial field		•	F0		Select the type for the first field output after
		•	F1		reset, or after a resolution change.
Passthrough mode		On or Off			• Turn on to propagate interlaced fields
					unchanged.
					• Turn off to discard the interlaced input.
Run-time control (enable/disable		On or Off			Turn on to enable run-time control.
frame interlacing at run-time)
Control packets override field		On or Off			Turn on when the content of the control
selection					packet specifies which lines to drop when
					converting a progressive frame into an
					interlaced field.

Interlacer Signals

Table 16-2: Interlacer Common Signals

Signal		Directio		Description
		n

	clock		Input	The main system clock. The IP core operates on the
				rising edge of this signal.
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	Signal		Directio		Description
			n
	reset		Input		The IP core asynchronously resets when this signal is
					high. You must deassert this signal synchronously to the
					rising edge of the clock signal.
	din_data		Input		din port Avalon-ST data bus. This bus enables the
					transfer of pixel data into the IP core.
	din_endofpacket		Input		din port Avalon-ST endofpacket signal. This signal
					marks the end of an Avalon-ST packet.
	din_ready		Output		din port Avalon-ST ready signal. This signal indicates
					when the IP core is ready to receive data.
	din_startofpacket		Input		din port Avalon-ST startofpacket signal. This signal
					marks the start of an Avalon-ST packet.
	din_valid		Input		din port Avalon-ST valid signal. This signal identifies
					the cycles when the port must enter data.
	dout_data		Output		dout port Avalon-ST data bus. This bus enables the
					transfer of pixel data out of the IP core.
	dout_endofpacket		Output		dout port Avalon-ST endofpacket signal. This signal
					marks the end of an Avalon-ST packet.
	dout_ready		Input		dout port Avalon-ST ready signal. The downstream
					device asserts this signal when it is able to receive data.
	dout_startofpacket		Output		dout port Avalon-ST startofpacket signal. This signal
					marks the start of an Avalon-ST packet.
	dout_valid		Output		dout port Avalon-ST valid signal. The IP core asserts
					this signal when it produces data.
	Table 16-3: Interlacer Control Interface Signals

These signals are present only if you turn on Pass-through mode.

Signal		Directio		Description
		n

control_av_address	Input	control slave port Avalon-MM address bus. This bus
		specifies a word offset into the slave address space.
control_av_chipselect	Input	control slave port Avalon-MM chipselect signal. The
		control port ignores all other signals unless you assert
		this signal.
control_av_readdata	Output	control slave port Avalon-MM readdata bus. The IP
		core uses these output lines for read transfers.
control_av_waitrequest	Output	control slave port Avalon-MM waitrequest signal.

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	16-4	Interlacer Control Registers	UG-VIPSUITE
			2015.01.23

Signal		Directio		Description
		n

control_av_write	Input	control slave port Avalon-MM write signal. When you
		assert this signal, the control port accepts new data from
		the writedata bus.
control_av_writedata	Input	control slave port Avalon-MM writedata bus. The IP
		core uses these input lines for write transfers.

Interlacer Control Registers

Table 16-4: Interlacer Register Map

The control interface is 8 bits wide but the Interlacer IP core only uses bit 0 of each addressable register.

Address		Register		Description
0		Control		Bit 0 of this register is the Go bit. All other bits are unused.
				Setting this bit to 1 causes the IP core to pass data through
				without modification.
1		Status		Bit 0 of this register is the Status bit, all other bits are unused.
2		Progressive pass-		Setting bit 0 to 1 disables the Interlacer IP core. When
		through		disabled, progressive inputs are propagated without modifica
				tion.

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