8-6	Video Clipping Control Registers	UG-VIPSUITE
			2015.01.23

Signal		Directio		Description
		n
control_byteenable		Input		control slave port Avalon-MM byteenable bus. This
				bus enables specific byte lane or lanes during transfers.
				Each bit in byteenable corresponds to a byte in
				writedata and readdata.
				During writes, byteenable specifies which bytes are
				being written to; other bytes are ignored by the slave.
				Slaves that simply return readdata with no side effects
				are free to ignore byteenable during reads.
control_read		Output		control slave port Avalon-MM read signal. When you
				assert this signal, the control port sends new data at
				readdata.
control_readdata		Output		control slave port Avalon-MM control_data bus. The
				IP core uses these output lines for read transfers.
control_readdatavalid		Output		control slave port Avalon-MM readdata bus. When
				you assert this signal, the control port sends new data at
				control_readdata.
control_waitrequest		Output		control slave port Avalon-MM waitrequest signal.
control_write		Input		control slave port Avalon-MM write signal. When you
				assert this signal, the control port accepts new data from
				the writedata bus.
control_writedata		Input		control slave port Avalon-MM writedata bus. The IP
				core uses these input lines for write transfers.

Video Clipping Control Registers

Table 8-6: Clipper Control Register Map

The control data is read once at the start of each frame and is buffered inside the IP core, so the registers can be safely updated during the processing of a frame.

Note: All Clipper registers are write-only except at address 1.

	Address			Register		Description
0				Control		Bit 0 of this register is the Go bit, all other bits are unused.
						Setting this bit to 0 causes the IP core to stop the next time
						control information is read.
	1			Status		Bit 0 of this register is the Status bit, all other bits are unused.
						The Clipper IP core sets this address to 0 between frames. It is
						set to 1 while the IP core is processing data and cannot be
						stopped.
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UG-VIPSUITE					Video Clipping Control Registers	8-7
2015.01.23
	Address		Register		Description
2			Left Offset		The left offset, in pixels, of the clipping window/rectangle.
					Note: The left and right offset values must be less than or
					equal to the input image width.
	3		Right Offset or		In clipping window mode, the right offset of the window. In
			Width		clipping rectangle mode, the width of the rectangle.
					Note: The left and right offset values must be less than or
					equal to the input image width.
4			Top Offset		The top offset, in pixels, of the clipping window/rectangle.
					Note: The top and bottom offset values must be less than
					or equal to the input image height.
	5		Bottom Offset or		In clipping window mode, the bottom offset of the window. In
			Height		clipping rectangle mode, the height of the rectangle.
					Note: The top and bottom offset values must be less than
					or equal to the input image height.
	Table 8-7: Clipper II Control Register Map

The control data is read once at the start of each frame and is buffered inside the IP core, so the registers can be safely updated during the processing of a frame.

Note: The run-time control register map for the Clipper II IP core is altered and does not match the register map of the Clipper IP core.

Address		Register		Description
0		Control		Bit 0 of this register is the Go bit, all other bits are unused.
				Setting this bit to 0 causes the IP core to stop the next time
				control information is read.
1		Status		Bit 0 of this register is the Status bit, all other bits are unused.
				The Clipper IP core sets this address to 0 between frames. It is
				set to 1 while the IP core is processing data and cannot be
				stopped.
2		Interrupt		This bit is not used because the IP core does not generate any
				interrupts.
3		Left Offset		The left offset, in pixels, of the clipping window/rectangle.
				Note: The left and right offset values must be less than or
				equal to the input image width.

Video Clipping IP Cores	Altera Corporation

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	8-8		Video Clipping Control Registers				UG-VIPSUITE
						2015.01.23
			Address		Register		Description
	4				Right Offset or		In clipping window mode, the right offset of the window. In
					Width		clipping rectangle mode, the width of the rectangle.
							Note: The left and right offset values must be less than or
							equal to the input image width.
		5			Top Offset		The top offset, in pixels, of the clipping window/rectangle.
							Note: The top and bottom offset values must be less than
							or equal to the input image height.
	6				Bottom Offset or		In clipping window mode, the bottom offset of the window. In
					Height		clipping rectangle mode, the height of the rectangle.
							Note: The top and bottom offset values must be less than
							or equal to the input image height.

Altera Corporation	Video Clipping IP Cores

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