UG-VIPSUITE	Chroma Resampler Signals	7-5
	2015.01.23

Chroma Resampler Signals

Table 7-2: Chroma Resampler Signals

Signal		Directio		Description
		n
clock		Input		The main system clock. The IP core operates on the
				rising edge of this signal.
reset		Input		The IP core asynchronously resets when this signal is
				high. You must deassert this signal synchronously to the
				rising edge of the clock signal.
din_data		Input		din port Avalon-ST data bus. This bus enables the
				transfer of pixel data into the IP core.
din_endofpacket		Input		din port Avalon-ST endofpacket signal. This signal
				marks the end of an Avalon-ST packet.
din_ready		Output		din port Avalon-ST ready signal. This signal indicates
				when the IP core is ready to receive data.
din_startofpacket		Input		din port Avalon-ST startofpacket signal. This signal
				marks the start of an Avalon-ST packet.
din_valid		Input		din port Avalon-ST valid signal. This signal identifies
				the cycles when the port must enter data.
dout_data		Output		dout port Avalon-ST data bus. This bus enables the
				transfer of pixel data out of the IP core.
dout_endofpacket		Output		dout port Avalon-ST endofpacket signal. This signal
				marks the end of an Avalon-ST packet.
dout_ready		Input		dout port Avalon-ST ready signal. The downstream
				device asserts this signal when it is able to receive data.
dout_startofpacket		Output		dout port Avalon-ST startofpacket signal. This signal
				marks the start of an Avalon-ST packet.
dout_valid		Output		dout port Avalon-ST valid signal. The IP core asserts
				this signal when it produces data.

Chroma Resampler IP Core	Altera Corporation

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