UG-VIPSUITE	Deinterlacing Control Registers	12-23
	2015.01.23

Signal		Directio		Description
		n
motion_write_master_write		Output		motion_write_master port Avalon-MM write signal.
				The IP core asserts this signal to indicate write requests
				from the master to the system interconnect fabric.
motion_write_master_burstcount		Output		motion_write_master port Avalon-MM burstcount
				signal. This signal specifies the number of transfers in
				each burst.
motion_write_master_writedata		Output		motion_write_master port Avalon-MM writedata bus.
				These output lines carry data for write transfers.
motion_write_master_		Input		motion_write_master port Avalon-MM waitrequest
waitrequest				signal. The system interconnect fabric asserts this signal
				to cause the master port to wait.

Deinterlacing Control Registers

Table 12-7: Deinterlacer Control Register Map for Run-Time Control of the Motion-Adaptive Algorithm

The table below describes the control register map that controls the motion-adaptive algorithm at run time. The control data is read once and registered before outputting a frame. It can be safely updated during the processing of a frame.

Address		Register		Description
0		Control		Bit 0 of this register is the Go bit, all other bits are unused.
				• Setting this bit to 0 causes Deinterlacer IP core to stop
				before control information is read and before producing a
				frame.
				• While stopped, the Deinterlacer IP core may continue to
				receive and drop frames at its input if triple-buffering is
				enabled.
1		Status		Bit 0 of this register is the Status bit, all other bits are unused.
2		Motion value		Write-only register.
		override		Bit 0 of this register must be set to 1 to override the per-pixel
				motion value computed by the deinterlacing algorithm with a
				user specified value. This register cannot be read.
3		Blending coefficient		Write-only register.
				The 16-bit value that overrides the motion value computed by
				the deinterlacing algorithm. This value can vary between 0
				(weaving) to 65535 (bobbing). The register cannot be read.

Deinterlacing IP Cores	Altera Corporation

Send Feedback

	12-24	Deinterlacing Control Registers	UG-VIPSUITE
			2015.01.23

Table 12-8: Deinterlacer Control Register Map for Synchronizing the Input and Output Frame Rates

The table below describes the control register map that synchronizes the input and output frame rates. The control data is read and registered when receiving the image data header that signals new frame. It can be safely updated during the processing of a frame.

Note: The behavior of the rate conversion algorithm is not directly affected by a particular choice of input and output rates but only by their ratio. 23.976—29.970 is equivalent to 24—30.

Address		Register		Description
0		Control		Bit 0 of this register is the Go bit, all other bits are unused.
				• Setting this bit to 0 causes the Deinterlacer IP core to stop
				before control information is read and before receiving
				and buffering the next frame.
				• While stopped, the Deinterlacer IP core may freeze the
				output and repeat a static frame if triple-buffering is
				enabled.
1		Status		Bit 0 of this register is the Status bit, all other bits are unused.
2		Input frame rate		Write-only register.
				An 8-bit integer value for the input frame rate. This register
				cannot be read.
3		Output frame rate		Write-only register.
				An 8-bit integer value for the output frame rate. This register
				cannot be read.

Table 12-9: Deinterlacer II Control Register Map for Run-Time Control of the Motion-Adaptive Algorithm

The table below describes the control register map that controls the motion-adaptive algorithm at run time. The control data is read once and registered before outputting a frame. It can be safely updated during the processing of a frame.

	Address			Register		Description
0				Control		Bit 0 of this register is the Go bit, all other bits are unused.
						Setting this bit to 0 causes the Deinterlacer II IP core to stop
						after generating the current output frame.
	1			Status		Bit 0 of this register is the Status bit, all other bits are unused.
						When this bit is set to 0, it either gets disabled through the Go
						bit or waits to receive video data.
2				Reserved		This register is reserved for future use.
	3			Cadence detect on		• Setting bit 0 of this register to 1 enables cadence detection.
						• Setting bit 0 of this register to 0 disables cadence detection.
						• Cadence detection is disabled on reset.
Altera Corporation						Deinterlacing IP Cores
						Send Feedback

UG-VIPSUITE					Deinterlacing Control Registers	12-25
2015.01.23
	Address		Register		Description
4			Cadence detected		• Reading a 1 from bit 0, indicates that the Deinterlacer II IP
					core has detected a cadence and is performing reverse
					telecine.
					• Reading a 0 indicates otherwise.

Table 12-10: Broadcast Deinterlacer Control Register Map

The table below describes the Broadcast Deinterlacer IP core control register map for runtime control of the motion-adaptive algorithm. The Broadcast Deinterlacer reads the control data once at the start of each frame and buffers the data inside the IP core. The registers may safely update during the processing of a frame. Use these registers in software to obtain the best deinterlacing quality.

Address		Register		RO/RW		Description
0		Control		RW		Bit 0 of this register is the Go bit, all other bits are
						unused.
						Setting this bit to 0 causes the Broadcast Deinterlacer
						IP core to stop the next time that control information
						is read.
						Power on value: 0
1		Status		RO		Bit 0 of this register is the Status bit, all other bits are
						unused.
						• The Broadcast Deinterlacer IP core sets this address
						to 0 between frames when the Go bit is set to 0.
						• The Broadcast Deinterlacer IP core sets this address
						to 1 while the core is processing data and cannot be
						stopped.
						Power on value: 0
2		Reserved		RO		This register is reserved for future use.
3		Cadence Detected		RO		• When polled, the least significant bit (LSB) to 1,
						indicates the Broadcast Deinterlacer IP core has
						detected a 3:3 or 2:2 cadence and is performing
						reverse telecine.
						• Bit 0 indicates otherwise.
						Range: 0–1
						Power on value: 0

Deinterlacing IP Cores	Altera Corporation

Send Feedback

12-26		Deinterlacing Control Registers						UG-VIPSUITE
							2015.01.23
		Address		Register		RO/RW		Description
		4		3:2 Cadence State		RO		Indicates overall 3:2 cadence state. May be a decoder to
				(VOF State)				determine whether the core is performing a weave with
								previous or incoming field.
								• 0 indicates that no 3:2 cadence is detected.
								• 2 indicates weave with previous field.
								• 3 indicates weave with incoming field.
								Range: 0–3
								Power on value: 0
		5		3:2 Cadence Film		RO		Number of pixels displaying film content in a given
				Pixels locked				field.
								Range: 0–(232–1)
								Power on value: 0
		6		Motion in field		RO		Total motion detected in the current field, computed
								from the sum of absolute differences (SAD) in Luma to
								the previous field of the same type, plus the Luma SAD
								of the previous field, and the next field, divided by 16.
								Range: 0–(232–1)
								Power on value: 0
		7		3:2 Cadence VOF				Histogram of locked pixels, that is used for debugging
				Histogram Total				purposes before the VOF lock. Indicates the number of
				Phase 1				pixels showing the presence of a potential cadence for
								this phase. If one phasing shows more pixels with a
		8		3:2 Cadence VOF
								cadence present compared to other phasing by a factor
				Histogram Total
								4 or more, all pixels in the field will be locked. Reverse
				Phase 2
								telecine on per-pixel basis will commence VOF Lock
		9		3:2 Cadence VOF		RO		Delay fields after the lock.
				Histogram Total				Range: 0–(232–1)
				Phase 3
								Power on value: 0
		10		3:2 Cadence VOF
				Histogram Total
				Phase 4
		11		3:2 Cadence VOF
				Histogram Total
				Phase 5

Altera Corporation	Deinterlacing IP Cores

Send Feedback

UG-VIPSUITE							Deinterlacing Control Registers		12-27
2015.01.23
	Address		Register		RO/RW		Description
12			Cadence Detect On		RW		• Setting the LSB of this register to 1 enables cadence
							detection.
							• Setting the LSB of this register to 0 disables cadence
							detection.
							• Cadence detection is disabled on reset.
							Range: 0–1
							Power on value: 0
13			Video Threshold		RW		The most important register to tune the video over
							film features. Set lower values for more emphasis on
							video and higher values for more emphasis on film.
							Range: 0–255
							Power on value: 160
14			Film Lock		RW		3:2 cadence is rechecked at every 5th field.
			Threshold				• If a given pixel fulfils the requirements for a
							cadence on a given field, the core increments its
							lock count.
							• If the lock count reaches the value of this register,
							then the given pixel is locked.
							Set lower values for greater sensitivity to cadenced
							sequences. If lock is declared for a pixel, then the core
							performs reverse telecine during deinterlacing.
							Range: 3–7
							Power on value: 3
15			Film Unlock		RW		3:2 cadence is rechecked at every 5th field.
			Threshold				• If a given pixel fulfils the requirements for a
							cadence on a given field, the core decrements its
							lock count.
							• If the lock count reaches the value of this register,
							then the given pixel loses its lock.
							Set lower values to cater for bad edits and poor film
							qualities. The value for this register must be set lower
							than the Film Lock Threshold register. The core
							performs standard motion adaptive deinterlacing for
							unlocked pixels.
							Range: 0–5
							Power on value: 0
Deinterlacing IP Cores								Altera Corporation
	Send Feedback

12-28		Deinterlacing Control Registers						UG-VIPSUITE
							2015.01.23
		Address		Register		RO/RW		Description
		16		VOF Lock Delay		RW		Specifies the number of fields elapsed after the core
								detects a cadence, but before reverse telecine begins.
								The delay allows for any video to drop out. If you set a
								value less than five, the core locks to cadence quicker
								but costs potential film artefacts.
								Range: 0–31
								Power on value: 5
		17		Minimum Pixels		RW		Specifies the least number of pixels showing a cadence
				Locked				for lock to occur.
								Range: 0–(232–1)
								Power on value: 256
		18		Min Valid SAD		RW		When considering whether pixels should remain
				Value				locked, the SAD values less than this range are ignored.
								Set this value high to prevent film pixels from decaying
								over time if they do not show a strong 3:2 cadence.
								Range: 0–255
								Power on value: 1
		19		Scene Change		RW		The Broadcast Deinterlacer IP core detects scene
				Threshold/Bad Edit				changes or bad edits, and resets the cadence state
				Detection				accordingly. The default value of 2 indicates that if
								there is 2^2(4) times as much motion detected in the
								next field, then a new scene or bad edit is flagged.
								Range: 0–15
								Power on value: 2
		20		Reserved		RW		This register is reserved for future use.
		21		Minimum Pixel		RW		Once a video achieves cadence lock, every pixel in the
				Kernel SAD for				frame will either maintain or lose lock independently
				Field Repeats				from then on. If the SAD value is less than the value for
								this register, then its lock count will be incremented. If
								it is higher than this value, its lock count will either
								remain unchanged or be decremented (if less than min
								valid SAD value).
								Range: 0–255
								Power on value: 80

Altera Corporation	Deinterlacing IP Cores

Send Feedback

UG-VIPSUITE							Deinterlacing Control Registers	12-29
2015.01.23
	Address		Register		RO/RW		Description
22			History Minimum		RW		The cadence bias for a given pixel. Setting a lower value
			Value				biases the pixels toward film, and setting a higher value
							biases the pixels toward video. The pixel SAD values
							are scaled according to the recent history that gives the
							frames an affinity for their historical state.
							Range: 0–3
							Power on value: 3
23			History Maximum		RW		The cadence bias for a given pixel. Setting a lower value
			Value				bias the pixels toward film and setting a higher bias the
							pixels toward video. The value for this register must be
							higher than the value for the History Minimum Value
							register.
							Range: 3–7
							Power on value: 7
24			SAD Mask		RW		When detecting cadences, the SAD values are AND’ed
							with this value. This value allows the LSBs to be
							masked off to provide protection from noise.
							For example, use binary 11_1111_0000 to ignore the
							lower 4 bits of the SAD data when detecting cadences.
							This register works orthogonally from the Motion
							Shift register (Offset 25), which affects both motion
							calculation in general AND cadence detection.
							Range: 512–1023
							Power on value: 960

Deinterlacing IP Cores	Altera Corporation

Send Feedback