Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 8XC196EA microcontroller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

				CONTENTS
CHAPTER 1
GUIDE TO THIS MANUAL
1.1		MANUAL CONTENTS ..................................................................................................		1-1
1.2	NOTATIONAL CONVENTIONS AND TERMINOLOGY ...............................................			1-3
1.3		RELATED DOCUMENTS .............................................................................................		1-7
1.4		APPLICATION SUPPORT SERVICES .........................................................................		1-8
CHAPTER 2
ARCHITECTURAL OVERVIEW
2.1		TYPICAL APPLICATIONS ............................................................................................		2-1
2.2		MICROCONTROLLER FEATURES .............................................................................		2-1
2.3		FUNCTIONAL OVERVIEW ...........................................................................................		2-5
2.3.1			Core .........................................................................................................................	2-5
2.3.1.1			CPU .....................................................................................................................	2-6
2.3.1.2 Register Arithmetic-logic Unit (RALU) .................................................................				2-6
2.3.1.3			Register File ........................................................................................................	2-7
2.3.2			Memory Controller ...................................................................................................	2-8
2.4		INTERNAL TIMING .......................................................................................................		2-9
2.4.1 Clock and Power Management Logic ......................................................................				2-9
2.4.2			Internal Timing .......................................................................................................	2-10
2.4.2.1			Clock Failure Detection Logic ...........................................................................	2-12
2.4.2.2			External Timing .................................................................................................	2-12
2.4.2.3			Power Management Options .............................................................................	2-13
2.4.3			Internal Memory ....................................................................................................	2-13
2.4.4			Serial Debug Unit ...................................................................................................	2-14
2.4.5			Interrupt Service .....................................................................................................	2-14
2.5		INTERNAL PERIPHERALS ........................................................................................		2-15
2.5.1			I/O Ports .................................................................................................................	2-15
2.5.2			Serial I/O (SIO) Port ...............................................................................................	2-15
2.5.3 Synchronous Serial I/O (SSIO) Port .......................................................................				2-15
2.5.4 Event Processor Array (EPA) and Timer/Counters ................................................				2-16
2.5.5			Analog-to-digital Converter ....................................................................................	2-16
2.5.6			Pulse-width Modulator (PWM) ...............................................................................	2-16
2.5.7			Stack Overflow Module ..........................................................................................	2-16
2.5.8			Watchdog Timer .....................................................................................................	2-17
2.6		SPECIAL OPERATING MODES ................................................................................		2-17
2.7		CHIP CONFIGURATION REGISTERS ......................................................................		2-17

iii

8XC196EA USER’S MANUAL
CHAPTER 3
PROGRAMMING CONSIDERATIONS
3.1 OVERVIEW OF THE INSTRUCTION SET ...................................................................			3-1
3.1.1		BIT Operands ...........................................................................................................	3-2
3.1.2		BYTE Operands .......................................................................................................	3-2
3.1.3		SHORT-INTEGER Operands ...................................................................................	3-2
3.1.4		WORD Operands .....................................................................................................	3-3
3.1.5		INTEGER Operands ................................................................................................	3-3
3.1.6		DOUBLE-WORD Operands .....................................................................................	3-3
3.1.7		LONG-INTEGER Operands .....................................................................................	3-4
3.1.8		QUAD-WORD Operands .........................................................................................	3-4
3.1.9		Converting Operands ...............................................................................................	3-4
3.1.10		Conditional Jumps ...................................................................................................	3-5
3.1.11		Floating-Point Operations ........................................................................................	3-5
3.1.12		Extended Instructions ..............................................................................................	3-5
3.2	ADDRESSING MODES ................................................................................................		3-6
3.2.1		Direct Addressing .....................................................................................................	3-7
3.2.2		Immediate Addressing .............................................................................................	3-7
3.2.3		Indirect Addressing ..................................................................................................	3-8
3.2.3.1		Extended Indirect Addressing .............................................................................	3-8
3.2.3.2 Indirect Addressing with Autoincrement ..............................................................			3-8
3.2.3.3 Extended Indirect Addressing with Autoincrement ..............................................			3-9
3.2.3.4 Indirect Addressing with the Stack Pointer ..........................................................			3-9
3.2.4		Indexed Addressing .................................................................................................	3-9
3.2.4.1		Short-indexed Addressing ...................................................................................	3-9
3.2.4.2		Long-indexed Addressing .................................................................................	3-10
3.2.4.3		Extended Indexed Addressing ..........................................................................	3-10
3.2.4.4		Zero-indexed Addressing ..................................................................................	3-11
3.2.4.5		Extended Zero-indexed Addressing ..................................................................	3-11
3.3 CONSIDERATIONS FOR CROSSING PAGE BOUNDARIES ...................................			3-11
3.4 SOFTWARE PROTECTION FEATURES AND GUIDELINES ...................................			3-12
CHAPTER 4
MEMORY PARTITIONS
4.1	MEMORY MAP OVERVIEW .........................................................................................		4-1
4.2	MEMORY PARTITIONS ..............................................................................................		4-4
4.2.1		External Memory ......................................................................................................	4-5
4.2.2		Internal ROM ............................................................................................................	4-6
4.2.2.1 Program Memory in Page FFH ...........................................................................			4-7
4.2.2.2 Special-purpose Memory in Page FFH ...............................................................			4-7
4.2.2.3		Reserved Memory Locations ..............................................................................	4-8
4.2.2.4		Interrupt, PIH, and PTS Vectors ..........................................................................	4-9
4.2.2.5		Chip Configuration Bytes ....................................................................................	4-9
4.2.3		Internal RAM (Code RAM) .......................................................................................	4-9

			CONTENTS
4.2.4		Special-function Registers (SFRs) .........................................................................	4-10
4.2.4.1		Memory-mapped SFRs .....................................................................................	4-11
4.2.4.2		Peripheral SFRs ................................................................................................	4-11
4.2.5		Register File ...........................................................................................................	4-14
4.2.5.1		General-purpose Register RAM ........................................................................	4-16
4.2.5.2		Stack Pointer (SP) .............................................................................................	4-16
4.2.5.3 CPU Special-function Registers (SFRs) ............................................................			4-17
4.3	WINDOWING ..............................................................................................................		4-17
4.3.1		Selecting a Window ...............................................................................................	4-18
4.3.2 Addressing a Location Through a Window ............................................................			4-21
4.3.2.1		32-byte Windowing Example .............................................................................	4-22
4.3.2.2		64-byte Windowing Example .............................................................................	4-22
4.3.2.3		128-byte Windowing Example ...........................................................................	4-22
4.3.2.4		Unsupported Locations Windowing Example ....................................................	4-23
4.3.2.5 Using the Linker Locator to Set Up a Window ...................................................			4-23
4.3.3		Windowing and Addressing Modes ........................................................................	4-25
4.4	CONTROLLING READ ACCESS TO THE INTERNAL ROM ....................................		4-26
4.5	REMAPPING INTERNAL ROM .................................................................................		4-29
4.6	FETCHING CODE AND DATA IN THE 2-MBYTE AND 64-KBYTE MODES .............		4-31
CHAPTER 5
STACK OVERFLOW MODULE
5.1	FUNCTIONAL OVERVIEW ...........................................................................................		5-1
5.2	STACK OPERATIONS .................................................................................................		5-1
5.3	STACK OVERFLOW MODULE REGISTERS ..............................................................		5-2
5.4	PROGRAMMING THE STACK OVERFLOW MODULE ...............................................		5-3
5.4.1 Initializing the Stack Pointer .....................................................................................			5-3
5.4.2 Enabling the Stack Overflow Module and Specifying Stack Boundaries .................			5-3
CHAPTER 6
STANDARD AND PTS INTERRUPTS
6.1	OVERVIEW OF THE INTERRUPT CONTROL CIRCUITRY ........................................		6-1
6.2	INTERRUPT SIGNALS AND REGISTERS ..................................................................		6-4
6.3	INTERRUPT SOURCES, PRIORITIES, AND VECTOR ADDRESSES .......................		6-5
6.3.1 PIH Interrupt Sources, Priorities, and Vector Addresses .........................................			6-7
6.3.1.1 Using Software to Provide the Vector Address ...................................................			6-9
6.3.1.2 Providing the Vector Address in Response to a CPU Request .........................			6-11
6.3.2		Special Interrupts ...................................................................................................	6-13
6.3.2.1		Unimplemented Opcode ...................................................................................	6-13
6.3.2.2		Software Trap ....................................................................................................	6-14
6.3.2.3		NMI ....................................................................................................................	6-14
6.3.2.4		Stack Overflow ..................................................................................................	6-14
6.3.3		External Interrupt Signal ........................................................................................	6-14
6.3.4		Shared Interrupt Requests .....................................................................................	6-14

8XC196EA USER’S MANUAL
6.3.5		End-of-PTS Interrupts ............................................................................................	6-15
6.4	INTERRUPT LATENCY ..............................................................................................		6-15
6.4.1 Situations that Increase Interrupt Latency .............................................................			6-16
6.4.2		Calculating Latency ................................................................................................	6-16
6.4.2.1		Worst-case Interrupt Latency ............................................................................	6-17
6.4.2.2		PTS Interrupt Latency .......................................................................................	6-17
6.5	PROGRAMMING THE INTERRUPTS ........................................................................		6-18
6.5.1		Modifying Interrupt Priorities ..................................................................................	6-25
6.5.2 Determining the Source of an Interrupt ..................................................................			6-27
6.6	INITIALIZING THE PTS CONTROL BLOCKS ............................................................		6-30
6.6.1		Specifying the PTS Count ......................................................................................	6-31
6.6.2		Selecting the PTS Mode ........................................................................................	6-34
6.6.3		Single Transfer Mode .............................................................................................	6-35
6.6.4		Block Transfer Mode ..............................................................................................	6-38
6.6.5		Dummy Mode .........................................................................................................	6-40
6.6.6		Missed-Event Mode ...............................................................................................	6-41
CHAPTER 7
I/O PORTS
7.1	I/O PORTS OVERVIEW ...............................................................................................		7-1
7.2	CONFIGURING THE PORT PINS ................................................................................		7-7
7.2.1 Configuring Ports 2, 5, 7–12, and EPORT ...............................................................			7-7
7.2.2 Configuring Ports 3 and 4 (Address/Data Bus) ........................................................			7-8
7.2.3		Port Configuration Example ...................................................................................	7-10
7.3	USING THE SPECIAL-FUNCTION SIGNALS ............................................................		7-11
7.3.1 Address and Data Signals (Ports 3, 4, and EPORT) .............................................			7-11
7.3.1.1 EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold ............			7-12
7.3.2 Bus-control Signals (Ports 2 and 5) .......................................................................			7-12
7.3.3		Chip-select Signals (EPORT) .................................................................................	7-16
7.3.4 EPA and Timer Signals (Ports 7–10) .....................................................................			7-16
7.3.5 External Interrupt Signal (Port 2) ...........................................................................			7-18
7.3.6		PWM Signals (Port 11) ..........................................................................................	7-19
7.3.7 Serial I/O Port Signals (Ports 2 and 7) ...................................................................			7-19
7.3.8 Special Operating Mode Signal (Port 5 Pin 7) .......................................................			7-20
7.3.9 Synchronous Serial I/O Port Signals (Port 10) .......................................................			7-21
7.4	I/O PORT INTERNAL STRUCTURES ........................................................................		7-22
7.4.1 Internal Structure for the Extended I/O Port (EPORT Pins 0–4) ............................			7-22
7.4.2 Internal Structure for Ports 2, 5, 7–12, and EPORT Pins 5–7 ................................			7-24
7.4.3 Internal Structure for Ports 3 and 4 (Address/Data Bus) ........................................			7-26

				CONTENTS
CHAPTER 8
SERIAL I/O (SIO) PORT
8.1	SERIAL I/O (SIO) PORT FUNCTIONAL OVERVIEW			.................................................. 8-1
8.2	SERIAL I/O PORT SIGNALS AND REGISTERS .........................................................			8-4
8.3		SERIAL PORT MODES ................................................................................................		8-6
8.3.1			Synchronous Mode (Mode 0) ..................................................................................	8-6
8.3.2 Asynchronous Modes (Modes 1, 2, and 3) ..............................................................				8-7
8.3.2.1			Mode 1 ................................................................................................................	8-8
8.3.2.2			Mode 2 ................................................................................................................	8-9
8.3.2.3			Mode 3 ................................................................................................................	8-9
8.3.2.4			Multiprocessor Communications .......................................................................	8-10
8.4	PROGRAMMING THE SERIAL PORT .......................................................................			8-10
8.4.1 Configuring the Serial Port Pins .............................................................................				8-10
8.4.2			Programming the Control Register .........................................................................	8-11
8.4.3 Programming the Baud Rate and Clock Source ....................................................				8-13
8.4.4			Enabling the Serial Port Interrupts .........................................................................	8-16
8.4.5 Determining Serial Port Status ...............................................................................				8-16
CHAPTER 9
SYNCHRONOUS SERIAL I/O (SSIO) PORT
9.1		SSIO PORT OVERVIEW ..............................................................................................		9-1
9.1.1			Standard Mode ........................................................................................................	9-1
9.1.2			Duplex Mode ............................................................................................................	9-2
9.1.3			Channel-select Mode ...............................................................................................	9-3
9.2	SSIO PORT SIGNALS AND REGISTERS ...................................................................			9-5
9.3		SSIO PORT OPERATION ............................................................................................		9-8
9.3.1			Transmitting and Receiving Data .............................................................................	9-8
9.3.1.1 Normal Transfers (All Modes) .............................................................................				9-9
9.3.1.2 Handshaking Transfers (Standard Mode Only) .................................................				9-10
9.4	PROGRAMMING THE SSIO PORT ...........................................................................			9-11
9.4.1 Configuring the SSIO Port Pins .............................................................................				9-11
9.4.2			Configuring the SSIO Registers .............................................................................	9-12
9.4.2.1 The SSIO Baud (SSIO_BAUD) Register ...........................................................				9-12
9.4.2.2 The SSIO Control (SSIOx_CON) Register ........................................................				9-14
9.4.2.3 The SSIO 0 Clock (SSIO0_CLK) Register ........................................................				9-17
9.4.2.4 The SSIO 1 Clock (SSIO1_CLK) Register ........................................................				9-17
9.4.2.5 The SSIO Buffer (SSIOx_BUF) Register ...........................................................				9-19
9.4.3			Enabling the SSIO Interrupts .................................................................................	9-20
9.5		PROGRAMMING CONSIDERATIONS .......................................................................		9-21
9.5.1			Variable-width MSB ...............................................................................................	9-21
9.5.2			Standard Mode Considerations .............................................................................	9-22
9.5.3			Duplex Mode Considerations .................................................................................	9-22
9.5.4			Channel-select Mode Considerations ....................................................................	9-23

vii


8XC196EA USER’S MANUAL
CHAPTER 10
PULSE-WIDTH MODULATOR
10.1	PWM FUNCTIONAL OVERVIEW ...............................................................................		10-1
10.2	PWM SIGNALS AND REGISTERS ............................................................................		10-2
10.3	PWM OPERATION .....................................................................................................		10-4
10.4	PROGRAMMING THE FREQUENCY AND PERIOD .................................................		10-5
10.5	PROGRAMMING THE DUTY CYCLE ........................................................................		10-7
10.5.1		Sample Calculations ..............................................................................................	10-8
10.5.2 Reading the Current Value of the Down-counter ...................................................			10-8
10.5.3 Enabling the PWM Outputs ....................................................................................			10-9
10.5.4		Generating Analog Outputs .................................................................................	10-10
CHAPTER 11
EVENT PROCESSOR ARRAY (EPA)
11.1	EPA FUNCTIONAL OVERVIEW ................................................................................		11-1
11.2	EPA AND TIMER/COUNTER SIGNALS AND REGISTERS ......................................		11-2
11.3	TIMER/COUNTER FUNCTIONAL OVERVIEW ..........................................................		11-6
11.3.1 Timer Multiplexing on the Time Bus .......................................................................			11-8
11.4	EPA CHANNEL FUNCTIONAL OVERVIEW ..............................................................		11-9
11.4.1 Operating in Input Capture Mode .........................................................................			11-10
11.4.2 Operating in Output Compare Mode ....................................................................			11-12
11.4.3 Operating in Compare Mode with the Output/Simulcapture Channels ................			11-12
11.4.4 Generating a 32-bit Time Value ...........................................................................			11-12
11.4.5 Controlling a Pair of Adjacent Pins ......................................................................			11-13
11.5	PROGRAMMING THE EPA AND TIMER/COUNTERS ............................................		11-14
11.5.1 Configuring the EPA and Timer/Counter Signals .................................................			11-15
11.5.2		Programming the Timers ......................................................................................	11-15
11.5.3		Programming the Capture/Compare Channels ....................................................	11-19
11.5.4 Programming the Compare-only (Output/Simulcapture) Channels ......................			11-22
11.6	ENABLING THE EPA INTERRUPTS .......................................................................		11-25
11.7	DETERMINING EVENT STATUS .............................................................................		11-28
CHAPTER 12
ANALOG-TO-DIGITAL (A/D) CONVERTER
12.1	A/D CONVERTER FUNCTIONAL OVERVIEW ..........................................................		12-1
12.2	A/D CONVERTER SIGNALS AND REGISTERS .......................................................		12-2
12.3	A/D CONVERTER OPERATION ................................................................................		12-3
12.4	PROGRAMMING THE A/D CONVERTER .................................................................		12-4
12.4.1 Programming the A/D Test Register ......................................................................			12-5
12.4.2 Programming the A/D Result Register (for Threshold Detection Only) ..................			12-6
12.4.3 Programming the A/D Time Register .....................................................................			12-7
12.4.4 Programming the A/D Command Register .............................................................			12-9
12.4.5 Programming the A/D Scan Register ...................................................................			12-10

viii

				CONTENTS
12.4.6		Enabling the A/D Interrupt ....................................................................................		12-10
12.5	DETERMINING A/D STATUS AND CONVERSION RESULTS ...............................			12-11
12.6	DESIGN CONSIDERATIONS ...................................................................................			12-13
12.6.1 Designing External Interface Circuitry ..................................................................				12-14
12.6.1.1 Minimizing the Effect of High Input Source Resistance ...................................				12-15
12.6.1.2			Suggested A/D Input Circuit ............................................................................	12-16
12.6.1.3 Analog Ground and Reference Voltages ........................................................				12-16
12.6.2 Understanding A/D Conversion Errors .................................................................				12-17
CHAPTER 13
MINIMUM HARDWARE CONSIDERATIONS
13.1	MINIMUM CONNECTIONS ........................................................................................			13-1
13.1.1		Unused Inputs ........................................................................................................		13-2
13.1.2 I/O Port Pin Connections .......................................................................................				13-2
13.2	APPLYING AND REMOVING POWER ......................................................................			13-4
13.3	NOISE PROTECTION TIPS .......................................................................................			13-4
13.4	THE ON-CHIP OSCILLATOR CIRCUITRY ................................................................			13-5
13.5	USING AN EXTERNAL CLOCK SOURCE .................................................................			13-7
13.6	RESETTING THE MICROCONTROLLER ..................................................................			13-9
13.6.1 Generating an External Reset ..............................................................................				13-10
13.6.2 Issuing the Reset (RST) Instruction .....................................................................				13-12
13.6.3 Issuing an Illegal IDLPD Key Operand ................................................................				13-12
13.6.4		Enabling the Watchdog Timer ..............................................................................		13-12
13.6.5		Detecting Clock Failure ........................................................................................		13-13
13.7	IDENTIFYING THE RESET SOURCE ......................................................................			13-13
CHAPTER 14
SPECIAL OPERATING MODES
14.1	SPECIAL OPERATING MODE SIGNALS AND REGISTERS ....................................			14-1
14.2	REDUCING POWER CONSUMPTION ......................................................................			14-4
14.3	IDLE MODE ................................................................................................................			14-5
14.3.1 Enabling and Disabling Idle Mode .........................................................................				14-5
14.3.2 Entering and Exiting Idle Mode ..............................................................................				14-5
14.4	POWERDOWN MODE ...............................................................................................			14-6
14.4.1 Enabling and Disabling Powerdown Mode .............................................................				14-6
14.4.2		Entering Powerdown Mode ....................................................................................		14-6
14.4.3		Exiting Powerdown Mode ......................................................................................		14-6
14.4.3.1 Generating a Hardware Reset ..........................................................................				14-7
14.4.3.2			Asserting the External Interrupt Signal ..............................................................	14-7
14.4.3.3 Selecting an External Capacitor ........................................................................				14-9
14.5	ONCE MODE ............................................................................................................			14-11

8XC196EA USER’S MANUAL
CHAPTER 15
INTERFACING WITH EXTERNAL MEMORY
15.1	INTERNAL AND EXTERNAL ADDRESSES ..............................................................	15-1
15.2	EXTERNAL MEMORY INTERFACE SIGNALS AND REGISTERS ...........................	15-2
15.3	THE CHIP-SELECT UNIT ...........................................................................................	15-9


15.3.1 Defining Chip-select Address Ranges .................................................................			15-10
15.3.2		Controlling Bus Parameters .................................................................................	15-13
15.3.3 Chip-select Unit Initial Conditions ........................................................................			15-14
15.3.4		Programming the Chip-select Registers ..............................................................	15-14
15.3.5 Example of a Chip-select Setup ...........................................................................			15-15
15.4	CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES ......		15-16
15.5	BUS WIDTH AND MULTIPLEXING ..........................................................................		15-22
15.5.1 A 16-bit Example System .....................................................................................			15-24
15.5.2		16-bit Bus Timings ...............................................................................................	15-25
15.5.3		8-bit Bus Timings .................................................................................................	15-27
15.5.4 Comparison of Multiplexed and Demultiplexed Buses .........................................			15-29
15.6	WAIT STATES (READY CONTROL) ........................................................................		15-29
15.7	BUS-HOLD PROTOCOL ..........................................................................................		15-33
15.7.1		Enabling the Bus-hold Protocol ............................................................................	15-34
15.7.2		Disabling the Bus-hold Protocol ...........................................................................	15-34
15.7.3		Hold Latency ........................................................................................................	15-35
15.7.4		Regaining Bus Control .........................................................................................	15-35
15.8	WRITE-CONTROL MODES .....................................................................................		15-36
15.9	SYSTEM BUS AC TIMING SPECIFICATIONS ........................................................		15-40
15.9.1		Deferred Bus-cycle Mode ....................................................................................	15-41
15.9.2 Explanation of AC Symbols .................................................................................			15-42
15.9.3		AC Timing Definitions ..........................................................................................	15-43
CHAPTER 16
SERIAL DEBUG UNIT
16.1	SERIAL DEBUG UNIT (SDU) FUNCTIONAL OVERVIEW .........................................		16-1
16.2	SDU SIGNALS AND REGISTERS .............................................................................		16-2
16.3	SDU OPERATION ......................................................................................................		16-3
16.3.1		SDU State Machine ...............................................................................................	16-3
16.3.2 Code RAM Access State Machine .........................................................................			16-5
16.3.3		Minimizing Latency ................................................................................................	16-6
16.4	CODE RAM ACCESS .................................................................................................		16-7
16.4.1 Code RAM Data Transfer ......................................................................................			16-8
16.4.2		Code RAM Access Instructions ..............................................................................	16-8
16.4.3 Code RAM Data Transfer Example ......................................................................			16-12
16.5	SDU INTERFACE CONNECTOR .............................................................................		16-14

				CONTENTS
CHAPTER 17
USING THE TEST-ROM ROUTINES
17.1	SIGNALS AND REGISTERS ......................................................................................			17-1
17.2	MEMORY PROTECTION OPTIONS ..........................................................................			17-2
17.3	ENTERING TEST-ROM ROUTINES ..........................................................................			17-5
17.3.1		Power-up and Power-down Sequences .................................................................		17-5
17.3.1.1			Power-up Sequence ..........................................................................................	17-5
17.3.1.2			Power-down Sequence .....................................................................................	17-5
17.4	ROM-DUMP ROUTINE AND CIRCUIT ......................................................................			17-6
17.5	SERIAL PORT MODE ROUTINE ...............................................................................			17-7
17.5.1		Serial Port RISM ....................................................................................................		17-7
17.5.2 Serial Port Mode Circuit .........................................................................................				17-8
17.6	SDU RISM EXECUTION ROUTINE .........................................................................			17-10
17.6.1		SDU RISM Data Transfer .....................................................................................		17-12
17.6.1.1 SDU RISM Data Transfer Before ....................................................................				17-12
17.6.1.2 SDU RISM Data Transfer After .......................................................................				17-13
17.6.2		SDU RISM Execution Circuit ................................................................................		17-13
17.7	RISM COMMAND DESCRIPTIONS .........................................................................			17-15
17.8	EXECUTING PROGRAMS FROM REGISTER RAM ...............................................			17-16
17.9	RISM COMMAND EXAMPLES .................................................................................			17-17
17.9.1 Serial Port Mode RISM Read Command Example ..............................................				17-17
17.9.2 Serial Port Mode RISM Write Command Example ..............................................				17-17
17.9.3 SDU RISM Execution Write Command Example .................................................				17-19
17.9.4 SDU RISM Execution Go Command Example ....................................................				17-20
APPENDIX A
INSTRUCTION SET REFERENCE
APPENDIX B
SIGNAL DESCRIPTIONS
B.1	FUNCTIONAL GROUPINGS OF SIGNALS ................................................................			B-1
B.2	SIGNAL DESCRIPTIONS ............................................................................................			B-5
B.3	DEFAULT CONDITIONS ...........................................................................................			B-14

APPENDIX C

REGISTERS

GLOSSARY

1 / 1141 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 > Следующая >>>

Соседние файлы в предмете Электротехника

#
23.08.2013763.84 Кб465.PCB design and layout.pdf
#
23.08.2013625.4 Кб155.Reference.pdf
#
23.08.20133.76 Mб316.Experiments.pdf
#
23.08.2013355.24 Кб306.PID control.pdf
#
23.08.2013202.94 Кб147.Specifications.pdf
#
23.08.20138.29 Mб518xC196EA microcontroller user's manual.1998.pdf
#
23.08.20133.97 Mб568XC196Kx,8XC196Jx,87C196CA microcontroller family user's manual.1995.pdf
#
23.08.2013344.78 Кб21Aggarwal V.A self-tuning analog PID controller.pdf
#
23.08.2013516.91 Кб16Ait-Kaci H.Warren's abstract machine.A tutorial reconstruction.1999.pdf
#
23.08.20137.44 Mб16Albertos P.Multivariable control systems.An engineering approach.2004.pdf
#
23.08.2013489.88 Кб20Alford C.Digital design VHDL laboratory notes.1996.pdf

CONTENTS