8XC196EA USER’S MANUAL

Table 9-2. SSIO Port Registers (Continued)

Mnemonic	Address	Description
SSIO0_CLK	1F95H	SSIO 0 Clock
		Configures the serial clock for channel 0. It determines the idle state of
		the serial clock. For transmissions, SSIO0_CLK determines whether
		the SSIO shifts out data bits on rising or falling clock edges. For
		receptions, SSIO0_CLK determines whether the SSIO samples data
		bits on rising or falling clock edges.
		The serial clock is configurable only for normal transfers; therefore, this
		register is ignored for handshaking transfers.
SSIO1_CLK	1F97H	SSIO 1 Clock
		Selects the operating mode (standard, duplex, or channel select) and
		enables the channel-select mode’s master contention interrupt request.
		For normal transfers, this register configures the serial clock for
		channel 1. It determines the idle state of the serial clock. For
		transmissions, SSIO1_CLK determines whether the SSIO shifts out
		data bits on rising or falling clock edges. For receptions, SSIO1_CLK
		determines whether the SSIO samples data bits on the rising or falling
		clock edges.

9.3SSIO PORT OPERATION

The SSIO port contains two identical transceiver channels and a baud-rate generator. Each transceiver channel contains an 8-bit buffer register (SSIOx_BUF), a control register (SSIOx_CON), a data signal (SDx), and an interrupt signal (SSIOx). In standard mode, each channel contains a clock signal (SCx). In duplex and channel-select modes, the channels share a clock signal (SC0). Additionally, the SSIO port contains two registers (SSIO0_CLK and SSIO1_CLK) that select the operating mode and configure the serial clock signals.

9.3.1Transmitting and Receiving Data

The SSIO port can perform two types of data transfers: normal and handshaking. For normal transfers, the idle state of the serial clock and the serial clock edge on which the SSIO shifts out or samples data bits is programmable. For handshaking transfers, the slave device can pull the serial clock signal low to indicate that it is not ready.

All modes support normal transfers, while only standard mode supports handshaking transfers. For both transfer types, the serial clock controls the rate at which the SSIO shifts data bits out for transmissions and samples data bits for receptions. During transfers, eight pulses on the serial clock cause the SSIO to shift out or sample data bits; between transfers, the serial clock is held at its idle state. When the SSIO channel is configured as a master, the serial clock (SCx) signal is internally derived from the SSIO baud-rate generator. During transfers, the serial clock is synchronized with the baud clock and output on the serial clock (SCx) pin; between transfers, the SSIO channel drives the serial clock to its idle state. When the SSIO channel is configured as a slave, the serial clock signal is externally derived and input on the serial clock (SCx) pin.

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SYNCHRONOUS SERIAL I/O (SSIO) PORT

9.3.1.1Normal Transfers (All Modes)

For normal transfers, two conditions must be true for a transfer to begin: the transfer must be enabled and the SSIO buffer must be full for transmissions or empty for receptions. Once a transfer is initiated, the SSIO monitors SCx. The SSIO shifts data out during transmissions on falling SCx edges and samples data bits during receptions on rising SCx edges. The edge on which the SSIO shifts data out during transmissions and the edge on which the SSIO samples data bits during receptions is programmable. When the SSIO channel is configured as a master, after it shifts out or samples the least-significant data bit, it drives the serial clock to its programmed idle state. Figure 9-4 shows the four clock options for transmissions and Figure 9-5 shows the four clock options for receptions.

1

2

3

4

5

6

7

8

SCx

idle state = low shift edge = rising

SCx

idle state = high shift edge = rising

SCx

idle state = high shift edge = falling

SCx

idle state = low shift edge = falling

SDx

D7

D6

D5

D4

D3

D2

D1

D0

A4326-01

Figure 9-4. Serial Clock Options for Transmissions

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8XC196EA USER’S MANUAL

1

2

3

4

5

6

7

8

SCx

idle state = low sampling edge = falling

SCx

idle state = high sampling edge = falling

SCx

idle state = high sampling edge = rising

SCx

idle state = low sampling edge = rising

SDx

D7

D6

D5

D4

D3

D2

D1

D0

A4328-01

Figure 9-5. Serial Clock Options for Receptions

After the SSIO shifts out or samples its last data bit, it sets a flag in the SSIO control (SSIOx_CON) register, indicating the SSIO buffer status, and generates an SSIO interrupt request. If the channel was configured as transmitter, at the completion of the transmission, the SSIO can re-enable the channel as a transmitter, enable the channel as a receiver, or disable the channel. Similarly, if the channel was configured as a receiver, at the completion of the reception, the SSIO can re-enable the channel as a receiver, enable the channel as a transmitter, or disable the channel.

9.3.1.2Handshaking Transfers (Standard Mode Only)

For handshaking transfers, the clock signal is used with an open-drain configuration. Three conditions must be true for a transfer to begin: the transfer must be enabled, the SSIO buffer must be full for transmissions or empty for receptions, and the serial clock signal must be high. Once a transfer is initiated, the SSIO monitors SCx. For transmissions, the SSIO shifts data bits out on rising clock edges. For receptions, the SSIO samples data bits on falling clock edges. When the SSIO channel is configured as a master, after it shifts out or samples the least-significant data bit, it floats the serial clock signal. At this point, the serial clock signal is either pulled high by an external resistor or pulled low by an external slave. When the SSIO channel is configured as a

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