SERIAL DEBUG UNIT

16.3 SDU OPERATION

The SDU functional block diagram (Figure 16-2) illustrates the operation of the SDU module.

		SDU_Interrupt		CPU
			EMAB	MDB	Test ROM
					(1 Kbyte)
CRDCLK	Serial Debug		Code RAM
CRIN	Unit	CMAB	(3 Kbytes)
CROUT	Breakpoint	CMDB
CRBUSY#	Logic
				Reserved
					A3327-01

Figure 16-2. SDU Functional Block Diagram

Three internal data registers control the operation of the SDU:

•The code RAM address access (CR_ADDR) register specifies the code RAM address to be read or written. This register automatically increments after each transfer.

•The code RAM data access (CR_DATA) register functions as an internal buffer to transfer data to and from the code RAM.

•The breakpoint address access (BP_ADDR) register specifies the memory address from which you want to generate a TRAP instruction, instead of executing code.

The SDU uses the command (SDU_COM) register as a temporary storage location for command information that the master shifts in serially one bit at a time. The data transfer protocol for the SDU is always the command byte followed by up to four data bytes. A command byte counter tracks the number of data bytes expected until the next command byte.

The clock rate of the SDU is one-half the internal operating frequency (f/2). With a 32 MHz external clock (the maximum frequency), the internal operating frequency (f) is 16 MHz, so the SDU operates at 8 MHz.

16.3.1 SDU State Machine

The SDU state machine diagram (Figure 16-3) illustrates the serial data transfer decision-making process.

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8XC196EA USER’S MANUAL

Reset

Reset, SDU Idle State

Serial transfer

Serial Transfer State

in progress

Receive Parallel Transfer State

SDU Command Decode and Execute

Transmit Parallel Transfer State

A3308-01

Figure 16-3. SDU State Machine Diagram

The following is a step-by-step account of the internal SDU operation as outlined in Figure 16-3:

1.The SDU begins in its idle state. When the first bit (the start bit) on CRIN is a zero and a rising edge is detected on CRDCLK, a serial data transmission starts. For synchronization purposes, a start bit of zero indicates that the first data frame (eight bits) being shifted in is a valid command byte.

NOTE

If the SDU was left in an unknown state and your application is attempting to re-establish communication with the SDU, the master must send it a synchronization sequence. The synchronization sequence consists of six consecutive command bytes containing the reset SDU instruction, 01111111B (7FH). This six-command sequence resynchronizes the SDU, regardless of its last state.

2.Data is shifted out of the transmit buffer and into the receive buffer at the same time.

3.After the transfer is completed, data in the receive buffer is moved to an internal register (command register, data register, or address register) pointed to by a receive pointer. The handshake signal, CRBUSY#, is asserted.

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SERIAL DEBUG UNIT

4.If the new data frame is a command, it is decoded and the command byte counter is updated.

—If the new command is a code RAM data access command, control is transferred to the code RAM access state machine before resuming onto the next step. (Refer to “Code RAM Access State Machine” on page 16-5.)

—If the new data frame is not a command byte, the receive and transmit pointers are updated.

5.Data from the register accessed by the last command is loaded into the transmit buffer. After the transmit buffer is loaded, the CRBUSY# signal is deasserted and the SDU returns to its idle state.

16.3.2 Code RAM Access State Machine

The code RAM access state machine diagram (Figure 16-4) illustrates the decision-making process of the code RAM read/write operation.

	Write	Code RAM	Read
		Read or Write Operation?
		(Branch from SDU State
		Machine)

Code RAM Busy

Set CMAB from CR_ADDR and CMDB from CR_DATA.

Code RAM Idle

Activate byte or word write signal, disable MAB and MDB drivers.

Code RAM Busy

Set CMAB from CR_ADDR.

Code RAM Idle

Activate word read signal, load CMDB into CR_DATA.

Increment CR_ADDR

Return to

SDU State Machine

A3318-01

Figure 16-4. Code RAM Access State Machine Diagram

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8XC196EA USER’S MANUAL

The code RAM data access command allows the SDU to read and write the code RAM without CPU intervention. The following is a step-by-step account of the read and write operation as outlined in Figure 16-4:

1.Perform a code RAM read or write operation.

— If SDU_COM.1 is set, a write operation is performed.

The memory address is loaded onto the code RAM memory address bus (CMAB) from the CR_ADDR register.

Data is loaded onto the code RAM memory data bus (CMDB) from the CR_DATA register.

— If SDU_COM.1 is cleared, a read operation is performed.

The memory address is loaded onto the code RAM memory address bus (CMAB) from the CR_ADDR register.

2.Wait at least two CPU states for any user application code that is currently executing from the code RAM to complete.

3.Once the code RAM enters an idle state, the byte/word bit is activated (SDU_COM.0).

—For a write operation, bit zero set indicates a byte transfer and bit zero clear indicates a word transfer. The memory address bus (MAB) and memory data bus (MDB) drivers to the code RAM are disabled.

—For a read operation, a word transfer is performed by loading the CMDB into the

CR_DATA register. The read operation does not support byte transfers.

4.The CR_ADDR register is automatically incremented to set up the next data transfer.

5.Control is returned to the SDU state machine.

16.3.3 Minimizing Latency

The SDU can access the code RAM only when the bus controller is starting an access to memory other than code RAM (i.e., Flash or external memory). Accesses to register RAM do not count in most cases, since the CPU directly accesses the register file. Therefore, to minimize latency, it is necessary to understand what the bus controller is doing in the user application at all times.

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